Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050783 |
1 |
|
|
T32 |
164711 |
|
T33 |
14861 |
|
T34 |
573 |
| auto[1] |
7684393 |
1 |
|
|
T32 |
157281 |
|
T34 |
614 |
|
T50 |
676 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14615556 |
1 |
|
|
T32 |
260691 |
|
T33 |
14861 |
|
T34 |
678 |
| auto[1] |
3119620 |
1 |
|
|
T32 |
61301 |
|
T34 |
509 |
|
T50 |
303 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10031299 |
1 |
|
|
T32 |
161096 |
|
T33 |
14861 |
|
T34 |
540 |
| auto[1] |
7703877 |
1 |
|
|
T32 |
160896 |
|
T34 |
647 |
|
T50 |
620 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2300534 |
1 |
|
|
T32 |
51227 |
|
T34 |
53 |
|
T50 |
119 |
| auto[1] |
auto[0] |
auto[1] |
1563041 |
1 |
|
|
T32 |
31033 |
|
T34 |
274 |
|
T50 |
111 |
| auto[1] |
auto[1] |
auto[0] |
2283723 |
1 |
|
|
T32 |
48368 |
|
T34 |
85 |
|
T50 |
198 |
| auto[1] |
auto[1] |
auto[1] |
1556579 |
1 |
|
|
T32 |
30268 |
|
T34 |
235 |
|
T50 |
192 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |