Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10026662 |
1 |
|
|
T32 |
154992 |
|
T33 |
14861 |
|
T34 |
616 |
| auto[1] |
7708514 |
1 |
|
|
T32 |
167000 |
|
T34 |
571 |
|
T50 |
532 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14619501 |
1 |
|
|
T32 |
261774 |
|
T33 |
14861 |
|
T34 |
707 |
| auto[1] |
3115675 |
1 |
|
|
T32 |
60218 |
|
T34 |
480 |
|
T50 |
240 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10037062 |
1 |
|
|
T32 |
164739 |
|
T33 |
14861 |
|
T34 |
607 |
| auto[1] |
7698114 |
1 |
|
|
T32 |
157253 |
|
T34 |
580 |
|
T50 |
467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2285854 |
1 |
|
|
T32 |
44636 |
|
T34 |
79 |
|
T50 |
142 |
| auto[1] |
auto[0] |
auto[1] |
1561013 |
1 |
|
|
T32 |
27580 |
|
T34 |
266 |
|
T50 |
141 |
| auto[1] |
auto[1] |
auto[0] |
2296585 |
1 |
|
|
T32 |
52399 |
|
T34 |
21 |
|
T50 |
85 |
| auto[1] |
auto[1] |
auto[1] |
1554662 |
1 |
|
|
T32 |
32638 |
|
T34 |
214 |
|
T50 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |