Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10066513 |
1 |
|
|
T32 |
162819 |
|
T33 |
14861 |
|
T34 |
734 |
| auto[1] |
7668663 |
1 |
|
|
T32 |
159173 |
|
T34 |
453 |
|
T50 |
738 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14620206 |
1 |
|
|
T32 |
260901 |
|
T33 |
14861 |
|
T34 |
718 |
| auto[1] |
3114970 |
1 |
|
|
T32 |
61091 |
|
T34 |
469 |
|
T50 |
195 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10043229 |
1 |
|
|
T32 |
161835 |
|
T33 |
14861 |
|
T34 |
540 |
| auto[1] |
7691947 |
1 |
|
|
T32 |
160157 |
|
T34 |
647 |
|
T50 |
465 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2284901 |
1 |
|
|
T32 |
49814 |
|
T34 |
127 |
|
T50 |
104 |
| auto[1] |
auto[0] |
auto[1] |
1557358 |
1 |
|
|
T32 |
31250 |
|
T34 |
321 |
|
T50 |
65 |
| auto[1] |
auto[1] |
auto[0] |
2292076 |
1 |
|
|
T32 |
49252 |
|
T34 |
51 |
|
T50 |
166 |
| auto[1] |
auto[1] |
auto[1] |
1557612 |
1 |
|
|
T32 |
29841 |
|
T34 |
148 |
|
T50 |
130 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |