Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10020723 |
1 |
|
|
T32 |
163722 |
|
T33 |
14861 |
|
T34 |
540 |
| auto[1] |
7714453 |
1 |
|
|
T32 |
158270 |
|
T34 |
647 |
|
T50 |
514 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14620006 |
1 |
|
|
T32 |
259541 |
|
T33 |
14861 |
|
T34 |
773 |
| auto[1] |
3115170 |
1 |
|
|
T32 |
62451 |
|
T34 |
414 |
|
T50 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047162 |
1 |
|
|
T32 |
159835 |
|
T33 |
14861 |
|
T34 |
585 |
| auto[1] |
7688014 |
1 |
|
|
T32 |
162157 |
|
T34 |
602 |
|
T50 |
402 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2292533 |
1 |
|
|
T32 |
48391 |
|
T34 |
100 |
|
T50 |
97 |
| auto[1] |
auto[0] |
auto[1] |
1560638 |
1 |
|
|
T32 |
30491 |
|
T34 |
210 |
|
T50 |
112 |
| auto[1] |
auto[1] |
auto[0] |
2280311 |
1 |
|
|
T32 |
51315 |
|
T34 |
88 |
|
T50 |
106 |
| auto[1] |
auto[1] |
auto[1] |
1554532 |
1 |
|
|
T32 |
31960 |
|
T34 |
204 |
|
T50 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |