Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10050479 |
1 |
|
|
T32 |
168010 |
|
T33 |
14861 |
|
T34 |
559 |
| auto[1] |
7684697 |
1 |
|
|
T32 |
153982 |
|
T34 |
628 |
|
T50 |
499 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16757151 |
1 |
|
|
T32 |
300648 |
|
T33 |
14861 |
|
T34 |
1164 |
| auto[1] |
978025 |
1 |
|
|
T32 |
21344 |
|
T34 |
23 |
|
T50 |
63 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10041321 |
1 |
|
|
T32 |
160084 |
|
T33 |
14861 |
|
T34 |
481 |
| auto[1] |
7693855 |
1 |
|
|
T32 |
161908 |
|
T34 |
706 |
|
T50 |
365 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3377562 |
1 |
|
|
T32 |
73211 |
|
T34 |
308 |
|
T50 |
185 |
| auto[1] |
auto[0] |
auto[1] |
493061 |
1 |
|
|
T32 |
11120 |
|
T34 |
11 |
|
T50 |
37 |
| auto[1] |
auto[1] |
auto[0] |
3338268 |
1 |
|
|
T32 |
67353 |
|
T34 |
375 |
|
T50 |
117 |
| auto[1] |
auto[1] |
auto[1] |
484964 |
1 |
|
|
T32 |
10224 |
|
T34 |
12 |
|
T50 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |