Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10035532 |
1 |
|
|
T32 |
164614 |
|
T33 |
14861 |
|
T34 |
509 |
auto[1] |
7699644 |
1 |
|
|
T32 |
157378 |
|
T34 |
678 |
|
T50 |
687 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13161236 |
1 |
|
|
T32 |
221713 |
|
T33 |
14861 |
|
T34 |
1108 |
auto[1] |
4573940 |
1 |
|
|
T32 |
100279 |
|
T34 |
79 |
|
T50 |
274 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10043586 |
1 |
|
|
T32 |
160150 |
|
T33 |
14861 |
|
T34 |
725 |
auto[1] |
7691590 |
1 |
|
|
T32 |
161842 |
|
T34 |
462 |
|
T50 |
596 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1561392 |
1 |
|
|
T32 |
30449 |
|
T34 |
154 |
|
T50 |
134 |
auto[1] |
auto[0] |
auto[1] |
2288393 |
1 |
|
|
T32 |
50402 |
|
T34 |
26 |
|
T50 |
120 |
auto[1] |
auto[1] |
auto[0] |
1556258 |
1 |
|
|
T32 |
31114 |
|
T34 |
229 |
|
T50 |
188 |
auto[1] |
auto[1] |
auto[1] |
2285547 |
1 |
|
|
T32 |
49877 |
|
T34 |
53 |
|
T50 |
154 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10019379 |
1 |
|
|
T32 |
157132 |
|
T33 |
14861 |
|
T34 |
603 |
auto[1] |
7715797 |
1 |
|
|
T32 |
164860 |
|
T34 |
584 |
|
T50 |
553 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13156954 |
1 |
|
|
T32 |
218129 |
|
T33 |
14861 |
|
T34 |
1078 |
auto[1] |
4578222 |
1 |
|
|
T32 |
103863 |
|
T34 |
109 |
|
T50 |
262 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10041618 |
1 |
|
|
T32 |
155647 |
|
T33 |
14861 |
|
T34 |
734 |
auto[1] |
7693558 |
1 |
|
|
T32 |
166345 |
|
T34 |
453 |
|
T50 |
560 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1557618 |
1 |
|
|
T32 |
29747 |
|
T34 |
169 |
|
T50 |
182 |
auto[1] |
auto[0] |
auto[1] |
2289116 |
1 |
|
|
T32 |
49382 |
|
T34 |
47 |
|
T50 |
160 |
auto[1] |
auto[1] |
auto[0] |
1557718 |
1 |
|
|
T32 |
32735 |
|
T34 |
175 |
|
T50 |
116 |
auto[1] |
auto[1] |
auto[1] |
2289106 |
1 |
|
|
T32 |
54481 |
|
T34 |
62 |
|
T50 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10063015 |
1 |
|
|
T32 |
159322 |
|
T33 |
14861 |
|
T34 |
679 |
auto[1] |
7672161 |
1 |
|
|
T32 |
162670 |
|
T34 |
508 |
|
T50 |
539 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13145962 |
1 |
|
|
T32 |
218971 |
|
T33 |
14861 |
|
T34 |
1038 |
auto[1] |
4589214 |
1 |
|
|
T32 |
103021 |
|
T34 |
149 |
|
T50 |
360 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10026094 |
1 |
|
|
T32 |
157516 |
|
T33 |
14861 |
|
T34 |
573 |
auto[1] |
7709082 |
1 |
|
|
T32 |
164476 |
|
T34 |
614 |
|
T50 |
695 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1565278 |
1 |
|
|
T32 |
29687 |
|
T34 |
314 |
|
T50 |
169 |
auto[1] |
auto[0] |
auto[1] |
2305475 |
1 |
|
|
T32 |
49311 |
|
T34 |
99 |
|
T50 |
175 |
auto[1] |
auto[1] |
auto[0] |
1554590 |
1 |
|
|
T32 |
31768 |
|
T34 |
151 |
|
T50 |
166 |
auto[1] |
auto[1] |
auto[1] |
2283739 |
1 |
|
|
T32 |
53710 |
|
T34 |
50 |
|
T50 |
185 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10016247 |
1 |
|
|
T32 |
163620 |
|
T33 |
14861 |
|
T34 |
541 |
auto[1] |
7718929 |
1 |
|
|
T32 |
158372 |
|
T34 |
646 |
|
T50 |
717 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13166560 |
1 |
|
|
T32 |
222606 |
|
T33 |
14861 |
|
T34 |
1074 |
auto[1] |
4568616 |
1 |
|
|
T32 |
99386 |
|
T34 |
113 |
|
T50 |
245 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10053466 |
1 |
|
|
T32 |
161169 |
|
T33 |
14861 |
|
T34 |
607 |
auto[1] |
7681710 |
1 |
|
|
T32 |
160823 |
|
T34 |
580 |
|
T50 |
503 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1546339 |
1 |
|
|
T32 |
31783 |
|
T34 |
203 |
|
T50 |
76 |
auto[1] |
auto[0] |
auto[1] |
2274231 |
1 |
|
|
T32 |
51952 |
|
T34 |
51 |
|
T50 |
76 |
auto[1] |
auto[1] |
auto[0] |
1566755 |
1 |
|
|
T32 |
29654 |
|
T34 |
264 |
|
T50 |
182 |
auto[1] |
auto[1] |
auto[1] |
2294385 |
1 |
|
|
T32 |
47434 |
|
T34 |
62 |
|
T50 |
169 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10026588 |
1 |
|
|
T32 |
160006 |
|
T33 |
14861 |
|
T34 |
756 |
auto[1] |
7708588 |
1 |
|
|
T32 |
161986 |
|
T34 |
431 |
|
T50 |
639 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16763797 |
1 |
|
|
T32 |
300956 |
|
T33 |
14861 |
|
T34 |
1161 |
auto[1] |
971379 |
1 |
|
|
T32 |
21036 |
|
T34 |
26 |
|
T50 |
116 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10076827 |
1 |
|
|
T32 |
160413 |
|
T33 |
14861 |
|
T34 |
627 |
auto[1] |
7658349 |
1 |
|
|
T32 |
161579 |
|
T34 |
560 |
|
T50 |
596 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3357115 |
1 |
|
|
T32 |
67486 |
|
T34 |
276 |
|
T50 |
269 |
auto[1] |
auto[0] |
auto[1] |
487037 |
1 |
|
|
T32 |
10044 |
|
T34 |
20 |
|
T50 |
65 |
auto[1] |
auto[1] |
auto[0] |
3329855 |
1 |
|
|
T32 |
73057 |
|
T34 |
258 |
|
T50 |
211 |
auto[1] |
auto[1] |
auto[1] |
484342 |
1 |
|
|
T32 |
10992 |
|
T34 |
6 |
|
T50 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10002677 |
1 |
|
|
T32 |
167614 |
|
T33 |
14861 |
|
T34 |
529 |
auto[1] |
7732499 |
1 |
|
|
T32 |
154378 |
|
T34 |
658 |
|
T50 |
628 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16758861 |
1 |
|
|
T32 |
301433 |
|
T33 |
14861 |
|
T34 |
1167 |
auto[1] |
976315 |
1 |
|
|
T32 |
20559 |
|
T34 |
20 |
|
T50 |
77 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10061815 |
1 |
|
|
T32 |
163095 |
|
T33 |
14861 |
|
T34 |
646 |
auto[1] |
7673361 |
1 |
|
|
T32 |
158897 |
|
T34 |
541 |
|
T50 |
413 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3340151 |
1 |
|
|
T32 |
71495 |
|
T34 |
194 |
|
T50 |
159 |
auto[1] |
auto[0] |
auto[1] |
487281 |
1 |
|
|
T32 |
10751 |
|
T34 |
11 |
|
T50 |
40 |
auto[1] |
auto[1] |
auto[0] |
3356895 |
1 |
|
|
T32 |
66843 |
|
T34 |
327 |
|
T50 |
177 |
auto[1] |
auto[1] |
auto[1] |
489034 |
1 |
|
|
T32 |
9808 |
|
T34 |
9 |
|
T50 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10006069 |
1 |
|
|
T32 |
158718 |
|
T33 |
14861 |
|
T34 |
574 |
auto[1] |
7729107 |
1 |
|
|
T32 |
163274 |
|
T34 |
613 |
|
T50 |
536 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16750155 |
1 |
|
|
T32 |
300429 |
|
T33 |
14861 |
|
T34 |
1162 |
auto[1] |
985021 |
1 |
|
|
T32 |
21563 |
|
T34 |
25 |
|
T50 |
115 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9991289 |
1 |
|
|
T32 |
159272 |
|
T33 |
14861 |
|
T34 |
635 |
auto[1] |
7743887 |
1 |
|
|
T32 |
162720 |
|
T34 |
552 |
|
T50 |
575 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3353636 |
1 |
|
|
T32 |
68131 |
|
T34 |
200 |
|
T50 |
279 |
auto[1] |
auto[0] |
auto[1] |
487171 |
1 |
|
|
T32 |
10376 |
|
T34 |
10 |
|
T50 |
79 |
auto[1] |
auto[1] |
auto[0] |
3405230 |
1 |
|
|
T32 |
73026 |
|
T34 |
327 |
|
T50 |
181 |
auto[1] |
auto[1] |
auto[1] |
497850 |
1 |
|
|
T32 |
11187 |
|
T34 |
15 |
|
T50 |
36 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9999553 |
1 |
|
|
T32 |
166179 |
|
T33 |
14861 |
|
T34 |
685 |
auto[1] |
7735623 |
1 |
|
|
T32 |
155813 |
|
T34 |
502 |
|
T50 |
627 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16754049 |
1 |
|
|
T32 |
301556 |
|
T33 |
14861 |
|
T34 |
1165 |
auto[1] |
981127 |
1 |
|
|
T32 |
20436 |
|
T34 |
22 |
|
T50 |
108 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10015620 |
1 |
|
|
T32 |
166223 |
|
T33 |
14861 |
|
T34 |
641 |
auto[1] |
7719556 |
1 |
|
|
T32 |
155769 |
|
T34 |
546 |
|
T50 |
598 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3356891 |
1 |
|
|
T32 |
68278 |
|
T34 |
337 |
|
T50 |
222 |
auto[1] |
auto[0] |
auto[1] |
487584 |
1 |
|
|
T32 |
10223 |
|
T34 |
14 |
|
T50 |
51 |
auto[1] |
auto[1] |
auto[0] |
3381538 |
1 |
|
|
T32 |
67055 |
|
T34 |
187 |
|
T50 |
268 |
auto[1] |
auto[1] |
auto[1] |
493543 |
1 |
|
|
T32 |
10213 |
|
T34 |
8 |
|
T50 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10050783 |
1 |
|
|
T32 |
164711 |
|
T33 |
14861 |
|
T34 |
573 |
auto[1] |
7684393 |
1 |
|
|
T32 |
157281 |
|
T34 |
614 |
|
T50 |
676 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16757768 |
1 |
|
|
T32 |
301178 |
|
T33 |
14861 |
|
T34 |
1165 |
auto[1] |
977408 |
1 |
|
|
T32 |
20814 |
|
T34 |
22 |
|
T50 |
102 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10042560 |
1 |
|
|
T32 |
162575 |
|
T33 |
14861 |
|
T34 |
530 |
auto[1] |
7692616 |
1 |
|
|
T32 |
159417 |
|
T34 |
657 |
|
T50 |
527 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3370617 |
1 |
|
|
T32 |
68422 |
|
T34 |
245 |
|
T50 |
255 |
auto[1] |
auto[0] |
auto[1] |
491740 |
1 |
|
|
T32 |
10296 |
|
T34 |
5 |
|
T50 |
62 |
auto[1] |
auto[1] |
auto[0] |
3344591 |
1 |
|
|
T32 |
70181 |
|
T34 |
390 |
|
T50 |
170 |
auto[1] |
auto[1] |
auto[1] |
485668 |
1 |
|
|
T32 |
10518 |
|
T34 |
17 |
|
T50 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10017617 |
1 |
|
|
T32 |
166416 |
|
T33 |
14861 |
|
T34 |
476 |
auto[1] |
7717559 |
1 |
|
|
T32 |
155576 |
|
T34 |
711 |
|
T50 |
647 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16757596 |
1 |
|
|
T32 |
300483 |
|
T33 |
14861 |
|
T34 |
1165 |
auto[1] |
977580 |
1 |
|
|
T32 |
21509 |
|
T34 |
22 |
|
T50 |
136 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10049013 |
1 |
|
|
T32 |
158050 |
|
T33 |
14861 |
|
T34 |
636 |
auto[1] |
7686163 |
1 |
|
|
T32 |
163942 |
|
T34 |
551 |
|
T50 |
725 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3352777 |
1 |
|
|
T32 |
72201 |
|
T34 |
192 |
|
T50 |
252 |
auto[1] |
auto[0] |
auto[1] |
488350 |
1 |
|
|
T32 |
10934 |
|
T34 |
11 |
|
T50 |
57 |
auto[1] |
auto[1] |
auto[0] |
3355806 |
1 |
|
|
T32 |
70232 |
|
T34 |
337 |
|
T50 |
337 |
auto[1] |
auto[1] |
auto[1] |
489230 |
1 |
|
|
T32 |
10575 |
|
T34 |
11 |
|
T50 |
79 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10026662 |
1 |
|
|
T32 |
154992 |
|
T33 |
14861 |
|
T34 |
616 |
auto[1] |
7708514 |
1 |
|
|
T32 |
167000 |
|
T34 |
571 |
|
T50 |
532 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16757763 |
1 |
|
|
T32 |
300536 |
|
T33 |
14861 |
|
T34 |
1161 |
auto[1] |
977413 |
1 |
|
|
T32 |
21456 |
|
T34 |
26 |
|
T50 |
135 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10036707 |
1 |
|
|
T32 |
159907 |
|
T33 |
14861 |
|
T34 |
542 |
auto[1] |
7698469 |
1 |
|
|
T32 |
162085 |
|
T34 |
645 |
|
T50 |
679 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3363737 |
1 |
|
|
T32 |
70018 |
|
T34 |
294 |
|
T50 |
257 |
auto[1] |
auto[0] |
auto[1] |
489443 |
1 |
|
|
T32 |
10531 |
|
T34 |
13 |
|
T50 |
62 |
auto[1] |
auto[1] |
auto[0] |
3357319 |
1 |
|
|
T32 |
70611 |
|
T34 |
325 |
|
T50 |
287 |
auto[1] |
auto[1] |
auto[1] |
487970 |
1 |
|
|
T32 |
10925 |
|
T34 |
13 |
|
T50 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10016541 |
1 |
|
|
T32 |
165130 |
|
T33 |
14861 |
|
T34 |
428 |
auto[1] |
7718635 |
1 |
|
|
T32 |
156862 |
|
T34 |
759 |
|
T50 |
578 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16756233 |
1 |
|
|
T32 |
301234 |
|
T33 |
14861 |
|
T34 |
1164 |
auto[1] |
978943 |
1 |
|
|
T32 |
20758 |
|
T34 |
23 |
|
T50 |
100 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10039729 |
1 |
|
|
T32 |
163880 |
|
T33 |
14861 |
|
T34 |
584 |
auto[1] |
7695447 |
1 |
|
|
T32 |
158112 |
|
T34 |
603 |
|
T50 |
529 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3366260 |
1 |
|
|
T32 |
69945 |
|
T34 |
221 |
|
T50 |
249 |
auto[1] |
auto[0] |
auto[1] |
491262 |
1 |
|
|
T32 |
10686 |
|
T34 |
10 |
|
T50 |
60 |
auto[1] |
auto[1] |
auto[0] |
3350244 |
1 |
|
|
T32 |
67409 |
|
T34 |
359 |
|
T50 |
180 |
auto[1] |
auto[1] |
auto[1] |
487681 |
1 |
|
|
T32 |
10072 |
|
T34 |
13 |
|
T50 |
40 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10002687 |
1 |
|
|
T32 |
158764 |
|
T33 |
14861 |
|
T34 |
667 |
auto[1] |
7732489 |
1 |
|
|
T32 |
163228 |
|
T34 |
520 |
|
T50 |
809 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16759396 |
1 |
|
|
T32 |
302218 |
|
T33 |
14861 |
|
T34 |
1164 |
auto[1] |
975780 |
1 |
|
|
T32 |
19774 |
|
T34 |
23 |
|
T50 |
117 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10037620 |
1 |
|
|
T32 |
169022 |
|
T33 |
14861 |
|
T34 |
576 |
auto[1] |
7697556 |
1 |
|
|
T32 |
152970 |
|
T34 |
611 |
|
T50 |
580 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3353297 |
1 |
|
|
T32 |
63173 |
|
T34 |
337 |
|
T50 |
118 |
auto[1] |
auto[0] |
auto[1] |
486009 |
1 |
|
|
T32 |
9413 |
|
T34 |
9 |
|
T50 |
32 |
auto[1] |
auto[1] |
auto[0] |
3368479 |
1 |
|
|
T32 |
70023 |
|
T34 |
251 |
|
T50 |
345 |
auto[1] |
auto[1] |
auto[1] |
489771 |
1 |
|
|
T32 |
10361 |
|
T34 |
14 |
|
T50 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10066513 |
1 |
|
|
T32 |
162819 |
|
T33 |
14861 |
|
T34 |
734 |
auto[1] |
7668663 |
1 |
|
|
T32 |
159173 |
|
T34 |
453 |
|
T50 |
738 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16755851 |
1 |
|
|
T32 |
301468 |
|
T33 |
14861 |
|
T34 |
1163 |
auto[1] |
979325 |
1 |
|
|
T32 |
20524 |
|
T34 |
24 |
|
T50 |
80 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10029771 |
1 |
|
|
T32 |
165438 |
|
T33 |
14861 |
|
T34 |
531 |
auto[1] |
7705405 |
1 |
|
|
T32 |
156554 |
|
T34 |
656 |
|
T50 |
432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3362307 |
1 |
|
|
T32 |
67801 |
|
T34 |
354 |
|
T50 |
100 |
auto[1] |
auto[0] |
auto[1] |
489641 |
1 |
|
|
T32 |
10070 |
|
T34 |
10 |
|
T50 |
27 |
auto[1] |
auto[1] |
auto[0] |
3363773 |
1 |
|
|
T32 |
68229 |
|
T34 |
278 |
|
T50 |
252 |
auto[1] |
auto[1] |
auto[1] |
489684 |
1 |
|
|
T32 |
10454 |
|
T34 |
14 |
|
T50 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |