Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5342157	1			T22	1		T23	73		T1	729
all_pins[1]	5342157	1			T22	1		T23	73		T1	729
all_pins[2]	5342157	1			T22	1		T23	73		T1	729
all_pins[3]	5342157	1			T22	1		T23	73		T1	729
all_pins[4]	5342157	1			T22	1		T23	73		T1	729
all_pins[5]	5342157	1			T22	1		T23	73		T1	729
all_pins[6]	5342157	1			T22	1		T23	73		T1	729
all_pins[7]	5342157	1			T22	1		T23	73		T1	729
all_pins[8]	5342157	1			T22	1		T23	73		T1	729
all_pins[9]	5342157	1			T22	1		T23	73		T1	729
all_pins[10]	5342157	1			T22	1		T23	73		T1	729
all_pins[11]	5342157	1			T22	1		T23	73		T1	729
all_pins[12]	5342157	1			T22	1		T23	73		T1	729
all_pins[13]	5342157	1			T22	1		T23	73		T1	729
all_pins[14]	5342157	1			T22	1		T23	73		T1	729
all_pins[15]	5342157	1			T22	1		T23	73		T1	729
all_pins[16]	5342157	1			T22	1		T23	73		T1	729
all_pins[17]	5342157	1			T22	1		T23	73		T1	729
all_pins[18]	5342157	1			T22	1		T23	73		T1	729
all_pins[19]	5342157	1			T22	1		T23	73		T1	729
all_pins[20]	5342157	1			T22	1		T23	73		T1	729
all_pins[21]	5342157	1			T22	1		T23	73		T1	729
all_pins[22]	5342157	1			T22	1		T23	73		T1	729
all_pins[23]	5342157	1			T22	1		T23	73		T1	729
all_pins[24]	5342157	1			T22	1		T23	73		T1	729
all_pins[25]	5342157	1			T22	1		T23	73		T1	729
all_pins[26]	5342157	1			T22	1		T23	73		T1	729
all_pins[27]	5342157	1			T22	1		T23	73		T1	729
all_pins[28]	5342157	1			T22	1		T23	73		T1	729
all_pins[29]	5342157	1			T22	1		T23	73		T1	729
all_pins[30]	5342157	1			T22	1		T23	73		T1	729
all_pins[31]	5342157	1			T22	1		T23	73		T1	729

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	106179539	1			T22	32		T23	1263		T1	14175
values[0x1]	64769485	1			T23	1073		T1	9153		T11	243207
transitions[0x0=>0x1]	38810180	1			T23	561		T1	5381		T11	145910
transitions[0x1=>0x0]	38810038	1			T23	560		T1	5381		T11	145909

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3314981	1			T22	1		T23	48		T1	437
all_pins[0]	values[0x1]	2027176	1			T23	25		T1	292		T11	7722
all_pins[0]	transitions[0x0=>0x1]	1255277	1			T23	16		T1	169		T11	4681
all_pins[0]	transitions[0x1=>0x0]	1253893	1			T23	25		T1	184		T11	4714
all_pins[1]	values[0x0]	3324049	1			T22	1		T23	30		T1	438
all_pins[1]	values[0x1]	2018108	1			T23	43		T1	291		T11	7579
all_pins[1]	transitions[0x0=>0x1]	1207416	1			T23	25		T1	168		T11	4504
all_pins[1]	transitions[0x1=>0x0]	1216484	1			T23	7		T1	169		T11	4647
all_pins[2]	values[0x0]	3319031	1			T22	1		T23	29		T1	410
all_pins[2]	values[0x1]	2023126	1			T23	44		T1	319		T11	7137
all_pins[2]	transitions[0x0=>0x1]	1214119	1			T23	17		T1	197		T11	4378
all_pins[2]	transitions[0x1=>0x0]	1209101	1			T23	16		T1	169		T11	4820
all_pins[3]	values[0x0]	3313702	1			T22	1		T23	40		T1	446
all_pins[3]	values[0x1]	2028455	1			T23	33		T1	283		T11	7551
all_pins[3]	transitions[0x0=>0x1]	1212627	1			T23	15		T1	152		T11	4701
all_pins[3]	transitions[0x1=>0x0]	1207298	1			T23	26		T1	188		T11	4287
all_pins[4]	values[0x0]	3325295	1			T22	1		T23	49		T1	480
all_pins[4]	values[0x1]	2016862	1			T23	24		T1	249		T11	7648
all_pins[4]	transitions[0x0=>0x1]	1205718	1			T23	11		T1	131		T11	4635
all_pins[4]	transitions[0x1=>0x0]	1217311	1			T23	20		T1	165		T11	4538
all_pins[5]	values[0x0]	3318412	1			T22	1		T23	38		T1	399
all_pins[5]	values[0x1]	2023745	1			T23	35		T1	330		T11	7554
all_pins[5]	transitions[0x0=>0x1]	1214342	1			T23	24		T1	216		T11	4535
all_pins[5]	transitions[0x1=>0x0]	1207459	1			T23	13		T1	135		T11	4629
all_pins[6]	values[0x0]	3320413	1			T22	1		T23	42		T1	479
all_pins[6]	values[0x1]	2021744	1			T23	31		T1	250		T11	7960
all_pins[6]	transitions[0x0=>0x1]	1211075	1			T23	19		T1	106		T11	4745
all_pins[6]	transitions[0x1=>0x0]	1213076	1			T23	23		T1	186		T11	4339
all_pins[7]	values[0x0]	3315007	1			T22	1		T23	36		T1	443
all_pins[7]	values[0x1]	2027150	1			T23	37		T1	286		T11	7666
all_pins[7]	transitions[0x0=>0x1]	1215930	1			T23	21		T1	191		T11	4543
all_pins[7]	transitions[0x1=>0x0]	1210524	1			T23	15		T1	155		T11	4837
all_pins[8]	values[0x0]	3313134	1			T22	1		T23	29		T1	415
all_pins[8]	values[0x1]	2029023	1			T23	44		T1	314		T11	7802
all_pins[8]	transitions[0x0=>0x1]	1213634	1			T23	19		T1	195		T11	4518
all_pins[8]	transitions[0x1=>0x0]	1211761	1			T23	12		T1	167		T11	4382
all_pins[9]	values[0x0]	3318017	1			T22	1		T23	38		T1	473
all_pins[9]	values[0x1]	2024140	1			T23	35		T1	256		T11	7349
all_pins[9]	transitions[0x0=>0x1]	1209041	1			T23	17		T1	135		T11	4383
all_pins[9]	transitions[0x1=>0x0]	1213924	1			T23	26		T1	193		T11	4836
all_pins[10]	values[0x0]	3316847	1			T22	1		T23	49		T1	443
all_pins[10]	values[0x1]	2025310	1			T23	24		T1	286		T11	7718
all_pins[10]	transitions[0x0=>0x1]	1213920	1			T23	11		T1	204		T11	4818
all_pins[10]	transitions[0x1=>0x0]	1212750	1			T23	22		T1	174		T11	4449
all_pins[11]	values[0x0]	3315678	1			T22	1		T23	39		T1	442
all_pins[11]	values[0x1]	2026479	1			T23	34		T1	287		T11	7554
all_pins[11]	transitions[0x0=>0x1]	1211517	1			T23	25		T1	189		T11	4554
all_pins[11]	transitions[0x1=>0x0]	1210348	1			T23	15		T1	188		T11	4718
all_pins[12]	values[0x0]	3317096	1			T22	1		T23	43		T1	428
all_pins[12]	values[0x1]	2025061	1			T23	30		T1	301		T11	8040
all_pins[12]	transitions[0x0=>0x1]	1211773	1			T23	15		T1	189		T11	4926
all_pins[12]	transitions[0x1=>0x0]	1213191	1			T23	19		T1	175		T11	4440
all_pins[13]	values[0x0]	3316326	1			T22	1		T23	40		T1	442
all_pins[13]	values[0x1]	2025831	1			T23	33		T1	287		T11	7722
all_pins[13]	transitions[0x0=>0x1]	1210893	1			T23	19		T1	184		T11	4404
all_pins[13]	transitions[0x1=>0x0]	1210123	1			T23	16		T1	198		T11	4722
all_pins[14]	values[0x0]	3319945	1			T22	1		T23	44		T1	435
all_pins[14]	values[0x1]	2022212	1			T23	29		T1	294		T11	7273
all_pins[14]	transitions[0x0=>0x1]	1209572	1			T23	16		T1	153		T11	4267
all_pins[14]	transitions[0x1=>0x0]	1213191	1			T23	20		T1	146		T11	4716
all_pins[15]	values[0x0]	3317924	1			T22	1		T23	36		T1	497
all_pins[15]	values[0x1]	2024233	1			T23	37		T1	232		T11	7360
all_pins[15]	transitions[0x0=>0x1]	1210058	1			T23	25		T1	108		T11	4556
all_pins[15]	transitions[0x1=>0x0]	1208037	1			T23	17		T1	170		T11	4469
all_pins[16]	values[0x0]	3318191	1			T22	1		T23	43		T1	440
all_pins[16]	values[0x1]	2023966	1			T23	30		T1	289		T11	7623
all_pins[16]	transitions[0x0=>0x1]	1212336	1			T23	17		T1	200		T11	4821
all_pins[16]	transitions[0x1=>0x0]	1212603	1			T23	24		T1	143		T11	4558
all_pins[17]	values[0x0]	3321351	1			T22	1		T23	45		T1	435
all_pins[17]	values[0x1]	2020806	1			T23	28		T1	294		T11	7495
all_pins[17]	transitions[0x0=>0x1]	1207755	1			T23	12		T1	147		T11	4386
all_pins[17]	transitions[0x1=>0x0]	1210915	1			T23	14		T1	142		T11	4514
all_pins[18]	values[0x0]	3315311	1			T22	1		T23	33		T1	429
all_pins[18]	values[0x1]	2026846	1			T23	40		T1	300		T11	7653
all_pins[18]	transitions[0x0=>0x1]	1213316	1			T23	25		T1	143		T11	4516
all_pins[18]	transitions[0x1=>0x0]	1207276	1			T23	13		T1	137		T11	4358
all_pins[19]	values[0x0]	3321309	1			T22	1		T23	38		T1	422
all_pins[19]	values[0x1]	2020848	1			T23	35		T1	307		T11	7764
all_pins[19]	transitions[0x0=>0x1]	1207877	1			T23	14		T1	186		T11	4510
all_pins[19]	transitions[0x1=>0x0]	1213875	1			T23	19		T1	179		T11	4399
all_pins[20]	values[0x0]	3314957	1			T22	1		T23	37		T1	459
all_pins[20]	values[0x1]	2027200	1			T23	36		T1	270		T11	7981
all_pins[20]	transitions[0x0=>0x1]	1215709	1			T23	13		T1	159		T11	4669
all_pins[20]	transitions[0x1=>0x0]	1209357	1			T23	12		T1	196		T11	4452
all_pins[21]	values[0x0]	3325141	1			T22	1		T23	37		T1	471
all_pins[21]	values[0x1]	2017016	1			T23	36		T1	258		T11	7696
all_pins[21]	transitions[0x0=>0x1]	1205511	1			T23	12		T1	147		T11	4459
all_pins[21]	transitions[0x1=>0x0]	1215695	1			T23	12		T1	159		T11	4744
all_pins[22]	values[0x0]	3313944	1			T22	1		T23	37		T1	455
all_pins[22]	values[0x1]	2028213	1			T23	36		T1	274		T11	7142
all_pins[22]	transitions[0x0=>0x1]	1216938	1			T23	20		T1	157		T11	4191
all_pins[22]	transitions[0x1=>0x0]	1205741	1			T23	20		T1	141		T11	4745
all_pins[23]	values[0x0]	3315852	1			T22	1		T23	34		T1	382
all_pins[23]	values[0x1]	2026305	1			T23	39		T1	347		T11	7042
all_pins[23]	transitions[0x0=>0x1]	1210471	1			T23	18		T1	208		T11	4459
all_pins[23]	transitions[0x1=>0x0]	1212379	1			T23	15		T1	135		T11	4559
all_pins[24]	values[0x0]	3322921	1			T22	1		T23	38		T1	459
all_pins[24]	values[0x1]	2019236	1			T23	35		T1	270		T11	7416
all_pins[24]	transitions[0x0=>0x1]	1209224	1			T23	20		T1	127		T11	4679
all_pins[24]	transitions[0x1=>0x0]	1216293	1			T23	24		T1	204		T11	4305
all_pins[25]	values[0x0]	3320965	1			T22	1		T23	39		T1	427
all_pins[25]	values[0x1]	2021192	1			T23	34		T1	302		T11	7504
all_pins[25]	transitions[0x0=>0x1]	1209129	1			T23	12		T1	185		T11	4663
all_pins[25]	transitions[0x1=>0x0]	1207173	1			T23	13		T1	153		T11	4575
all_pins[26]	values[0x0]	3324272	1			T22	1		T23	47		T1	381
all_pins[26]	values[0x1]	2017885	1			T23	26		T1	348		T11	7659
all_pins[26]	transitions[0x0=>0x1]	1211149	1			T23	16		T1	211		T11	4615
all_pins[26]	transitions[0x1=>0x0]	1214456	1			T23	24		T1	165		T11	4460
all_pins[27]	values[0x0]	3314745	1			T22	1		T23	43		T1	464
all_pins[27]	values[0x1]	2027412	1			T23	30		T1	265		T11	7945
all_pins[27]	transitions[0x0=>0x1]	1214556	1			T23	19		T1	137		T11	4648
all_pins[27]	transitions[0x1=>0x0]	1205029	1			T23	15		T1	220		T11	4362
all_pins[28]	values[0x0]	3315150	1			T22	1		T23	44		T1	484
all_pins[28]	values[0x1]	2027007	1			T23	29		T1	245		T11	7504
all_pins[28]	transitions[0x0=>0x1]	1212604	1			T23	16		T1	157		T11	4260
all_pins[28]	transitions[0x1=>0x0]	1213009	1			T23	17		T1	177		T11	4701
all_pins[29]	values[0x0]	3311440	1			T22	1		T23	38		T1	468
all_pins[29]	values[0x1]	2030717	1			T23	35		T1	261		T11	7685
all_pins[29]	transitions[0x0=>0x1]	1215379	1			T23	20		T1	173		T11	4660
all_pins[29]	transitions[0x1=>0x0]	1211669	1			T23	14		T1	157		T11	4479
all_pins[30]	values[0x0]	3321910	1			T22	1		T23	42		T1	470
all_pins[30]	values[0x1]	2020247	1			T23	31		T1	259		T11	7707
all_pins[30]	transitions[0x0=>0x1]	1207012	1			T23	16		T1	169		T11	4577
all_pins[30]	transitions[0x1=>0x0]	1217482	1			T23	20		T1	171		T11	4555
all_pins[31]	values[0x0]	3316223	1			T22	1		T23	38		T1	422
all_pins[31]	values[0x1]	2025934	1			T23	35		T1	307		T11	7756
all_pins[31]	transitions[0x0=>0x1]	1214302	1			T23	16		T1	188		T11	4649
all_pins[31]	transitions[0x1=>0x0]	1208615	1			T23	12		T1	140		T11	4600