Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[1]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[2]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[3]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[4]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[5]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[6]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[7]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[8]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[9]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[10]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[11]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[12]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[13]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[14]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[15]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[16]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[17]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[18]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[19]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[20]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[21]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[22]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[23]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[24]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[25]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[26]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[27]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[28]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[29]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[30]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[31]	16887753	1			T22	284		T23	1162		T1	2026

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329859500

1

T22

6878

T23

19050

T1

49695

auto[1]

210548596

1

T22

2210

T23

18134

T1

15137

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430190523

1

T22

8249

T23

37184

T1

37168

auto[1]

110217573

1

T22

839

T1

27664

T11

487229

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398058695

1

T22

4500

T23

37184

T1

32761

auto[1]

142349401

1

T22

4588

T1

32071

T11

606003

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6294186	1			T22	98		T23	630		T1	552
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4407647	1			T22	38		T23	532		T1	23
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1732860	1			T22	14		T1	548		T11	7653
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2280401	1			T22	94		T1	427		T11	745
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	454845	1			T22	29		T1	23		T11	11276
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1717814	1			T22	11		T1	453		T11	7734
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6300833	1			T22	39		T23	611		T1	519
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4410523	1			T22	4		T23	551		T1	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1737027	1			T1	479		T11	7519		T12	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2273806	1			T22	192		T1	530		T11	625
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	453721	1			T22	39		T1	28		T11	10996
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1711843	1			T22	10		T1	456		T11	7502
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6290476	1			T22	65		T23	587		T1	585
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4415643	1			T22	23		T23	575		T1	22
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1728962	1			T22	10		T1	404		T11	7491
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2281168	1			T22	125		T1	637		T11	675
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	454054	1			T22	32		T1	32		T11	10732
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1717450	1			T22	29		T1	346		T11	7360
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6274649	1			T22	136		T23	581		T1	723
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4427232	1			T22	30		T23	581		T1	32
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1732812	1			T22	6		T1	501		T11	7927
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2281086	1			T22	79		T1	432		T11	643
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	454817	1			T22	25		T1	16		T11	10310
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1717157	1			T22	8		T1	322		T11	7817
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6279356	1			T22	153		T23	646		T1	515
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4419287	1			T22	52		T23	516		T1	14
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1730544	1			T22	26		T1	473		T11	7751
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2277689	1			T22	36		T1	593		T11	709
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	456961	1			T22	6		T1	30		T11	10788
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1723916	1			T22	11		T1	401		T11	7414
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6293633	1			T22	69		T23	552		T1	571
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4413118	1			T22	16		T23	610		T1	31
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1728543	1			T22	13		T1	460		T11	7618
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2280613	1			T22	128		T1	455		T11	654
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	451523	1			T22	39		T1	35		T11	10969
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1720323	1			T22	19		T1	474		T11	7892
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6290296	1			T22	139		T23	569		T1	543
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4410872	1			T22	29		T23	593		T1	26
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1736612	1			T22	15		T1	439		T11	7830
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2275240	1			T22	72		T1	623		T11	677
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	454192	1			T22	20		T1	18		T11	10411
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1720541	1			T22	9		T1	377		T11	7536
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6296552	1			T22	142		T23	579		T1	571
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4413009	1			T22	26		T23	583		T1	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1729014	1			T22	8		T1	420		T11	7866
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2277178	1			T22	75		T1	498		T11	681
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	454368	1			T22	18		T1	16		T11	10354
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1717632	1			T22	15		T1	492		T11	7801
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6295265	1			T22	140		T23	633		T1	533
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4414576	1			T22	43		T23	529		T1	35
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1739176	1			T22	20		T1	543		T11	7744
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2272281	1			T22	50		T1	508		T11	570
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	452102	1			T22	14		T1	16		T11	10560
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1714353	1			T22	17		T1	391		T11	7306
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6304041	1			T22	133		T23	559		T1	557
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4405063	1			T22	29		T23	603		T1	38
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1730092	1			T22	12		T1	513		T11	7229
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2277064	1			T22	75		T1	479		T11	671
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	452694	1			T22	20		T1	16		T11	10692
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1718799	1			T22	15		T1	423		T11	7513
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6297279	1			T22	27		T23	554		T1	580
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4407445	1			T22	6		T23	608		T1	45
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1729419	1			T22	5		T1	427		T11	7793
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2282493	1			T22	163		T1	512		T11	595
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	455127	1			T22	48		T1	11		T11	10456
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1715990	1			T22	35		T1	451		T11	7451
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6290996	1			T22	82		T23	616		T1	578
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4420889	1			T22	13		T23	546		T1	25
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1735864	1			T1	408		T11	7449		T13	52
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2267599	1			T22	124		T1	604		T11	601
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	451566	1			T22	36		T1	18		T11	10824
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1720839	1			T22	29		T1	393		T11	7932
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6298688	1			T22	104		T23	646		T1	397
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4408222	1			T22	23		T23	516		T1	5
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1737422	1			T22	4		T1	565		T11	7850
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2275627	1			T22	111		T1	533		T11	527
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	450918	1			T22	27		T1	29		T11	10241
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1716876	1			T22	15		T1	497		T11	7746
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6288917	1			T22	143		T23	549		T1	573
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4412352	1			T22	41		T23	613		T1	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1735295	1			T22	14		T1	384		T11	7772
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2277217	1			T22	61		T1	523		T11	667
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	454499	1			T22	19		T1	24		T11	11152
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1719473	1			T22	6		T1	499		T11	7455
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6289404	1			T22	110		T23	567		T1	654
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4413184	1			T22	29		T23	595		T1	14
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1742014	1			T22	21		T1	435		T11	7651
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2275576	1			T22	82		T1	555		T11	650
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	451310	1			T22	28		T1	27		T11	10632
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1716265	1			T22	14		T1	341		T11	7592
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6288205	1			T22	54		T23	577		T1	569
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4412410	1			T22	8		T23	585		T1	22
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1731597	1			T22	17		T1	443		T11	8041
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2281519	1			T22	152		T1	607		T11	648
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	454877	1			T22	45		T1	31		T11	10486
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1719145	1			T22	8		T1	354		T11	7603
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6291101	1			T22	79		T23	607		T1	542
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4420514	1			T22	20		T23	555		T1	29
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1726298	1			T22	6		T1	445		T11	7498
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2284843	1			T22	131		T1	532		T11	655
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	453783	1			T22	34		T1	17		T11	10973
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1711214	1			T22	14		T1	461		T11	7292
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6301780	1			T22	138		T23	561		T1	532
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4413298	1			T22	50		T23	601		T1	9
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1726029	1			T22	25		T1	451		T11	7967
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2283874	1			T22	53		T1	491		T11	587
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	453184	1			T22	11		T1	41		T11	10413
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1709588	1			T22	7		T1	502		T11	7100
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6294696	1			T22	84		T23	601		T1	456
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4406625	1			T22	21		T23	561		T1	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1730442	1			T1	380		T11	7828		T13	41
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2292267	1			T22	133		T1	673		T11	667
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	452432	1			T22	36		T1	26		T11	10550
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1711291	1			T22	10		T1	468		T11	7740
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6305536	1			T22	117		T23	488		T1	563
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4406675	1			T22	26		T23	674		T1	20
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1723748	1			T22	17		T1	452		T11	7770
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2283743	1			T22	86		T1	571		T11	613
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	455242	1			T22	30		T1	24		T11	10568
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1712809	1			T22	8		T1	396		T11	7428
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6306461	1			T22	65		T23	604		T1	585
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4408193	1			T22	23		T23	558		T1	21
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1726092	1			T22	20		T1	416		T11	7298
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2285133	1			T22	121		T1	577		T11	578
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	454127	1			T22	39		T1	24		T11	10885
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1707747	1			T22	16		T1	403		T11	7283
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6303976	1			T22	127		T23	557		T1	463
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4403363	1			T22	53		T23	605		T1	35
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1727007	1			T22	19		T1	420		T11	7794
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2288436	1			T22	56		T1	611		T11	728
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	456663	1			T22	13		T1	23		T11	10928
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1708308	1			T22	16		T1	474		T11	7701
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6287559	1			T22	42		T23	615		T1	604
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4422638	1			T22	9		T23	547		T1	22
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1726645	1			T22	2		T1	464		T11	7671
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2287565	1			T22	163		T1	579		T11	644
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	454942	1			T22	43		T1	33		T11	10692
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1708404	1			T22	25		T1	324		T11	8057
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6306258	1			T22	112		T23	523		T1	590
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4404335	1			T22	45		T23	639		T1	41
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1731102	1			T22	24		T1	370		T11	7922
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2284558	1			T22	72		T1	600		T11	681
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	453977	1			T22	24		T1	15		T11	10593
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1707523	1			T22	7		T1	410		T11	7250
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6309928	1			T22	156		T23	676		T1	564
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4399261	1			T22	47		T23	486		T1	29
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1730246	1			T22	12		T1	448		T11	7251
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2277942	1			T22	52		T1	488		T11	669
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	458959	1			T22	13		T1	22		T11	11562
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1711417	1			T22	4		T1	475		T11	7338
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6304725	1			T22	96		T23	605		T1	559
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4414926	1			T22	27		T23	557		T1	24
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1725797	1			T22	10		T1	442		T11	7576
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2281129	1			T22	116		T1	547		T11	772
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	452685	1			T22	26		T1	27		T11	11207
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1708491	1			T22	9		T1	427		T11	7201
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6291505	1			T22	66		T23	640		T1	610
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4420927	1			T22	19		T23	522		T1	18
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1723982	1			T22	8		T1	354		T11	8141
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2288802	1			T22	133		T1	705		T11	570
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	454470	1			T22	37		T1	20		T11	10336
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1708067	1			T22	21		T1	319		T11	7760
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6311263	1			T22	129		T23	597		T1	533
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4411279	1			T22	29		T23	565		T1	16
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1727078	1			T22	15		T1	412		T11	7781
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2278705	1			T22	78		T1	561		T11	695
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	448535	1			T22	19		T1	34		T11	10646
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1710893	1			T22	14		T1	470		T11	7654
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6301050	1			T22	67		T23	633		T1	562
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4411732	1			T22	14		T23	529		T1	20
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1730190	1			T22	12		T1	440		T11	7789
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2277552	1			T22	144		T1	543		T11	638
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	455226	1			T22	30		T1	27		T11	10694
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1712003	1			T22	17		T1	434		T11	7333
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6308164	1			T22	67		T23	563		T1	586
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4408435	1			T22	21		T23	599		T1	23
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1727866	1			T22	15		T1	337		T11	6963
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2280413	1			T22	133		T1	559		T11	623
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	455268	1			T22	30		T1	17		T11	11587
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1707607	1			T22	18		T1	504		T11	7500
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6304745	1			T22	58		T23	627		T1	634
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4406217	1			T22	17		T23	535		T1	41
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1727753	1			T22	11		T1	411		T11	7715
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2281913	1			T22	146		T1	552		T11	653
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	453974	1			T22	43		T1	20		T11	10861
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1713151	1			T22	9		T1	368		T11	7472
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6305823	1			T22	186		T23	697		T1	447
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4408326	1			T22	55		T23	465		T1	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1725605	1			T22	10		T1	412		T11	7641
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2285589	1			T22	28		T1	644		T11	557
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	454899	1			T22	3		T1	14		T11	10521
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1707511	1			T22	2		T1	463		T11	7677

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal