Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[1]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[2]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[3]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[4]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[5]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[6]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[7]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[8]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[9]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[10]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[11]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[12]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[13]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[14]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[15]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[16]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[17]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[18]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[19]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[20]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[21]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[22]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[23]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[24]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[25]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[26]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[27]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[28]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[29]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[30]	16887753	1			T22	284		T23	1162		T1	2026
bins_for_gpio_bits[31]	16887753	1			T22	284		T23	1162		T1	2026

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329859500

1

T22

6878

T23

19050

T1

49695

auto[1]

210548596

1

T22

2210

T23

18134

T1

15137

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329850729

1

T22

6878

T23

19050

T1

49688

auto[1]

210557367

1

T22

2210

T23

18134

T1

15144

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10000268	1			T22	202		T23	630		T1	1467
bins_for_gpio_bits[0]	auto[0]	auto[1]	306887	1			T22	4		T1	59		T11	1322
bins_for_gpio_bits[0]	auto[1]	auto[0]	307179	1			T22	4		T1	60		T11	1319
bins_for_gpio_bits[0]	auto[1]	auto[1]	6273419	1			T22	74		T23	532		T1	440
bins_for_gpio_bits[1]	auto[0]	auto[0]	10005517	1			T22	226		T23	611		T1	1458
bins_for_gpio_bits[1]	auto[0]	auto[1]	305901	1			T22	5		T1	70		T11	1347
bins_for_gpio_bits[1]	auto[1]	auto[0]	306149	1			T22	5		T1	70		T11	1340
bins_for_gpio_bits[1]	auto[1]	auto[1]	6270186	1			T22	48		T23	551		T1	428
bins_for_gpio_bits[2]	auto[0]	auto[0]	9993740	1			T22	193		T23	587		T1	1568
bins_for_gpio_bits[2]	auto[0]	auto[1]	306567	1			T22	7		T1	58		T11	1327
bins_for_gpio_bits[2]	auto[1]	auto[0]	306866	1			T22	7		T1	58		T11	1325
bins_for_gpio_bits[2]	auto[1]	auto[1]	6280580	1			T22	77		T23	575		T1	342
bins_for_gpio_bits[3]	auto[0]	auto[0]	9982293	1			T22	219		T23	581		T1	1609
bins_for_gpio_bits[3]	auto[0]	auto[1]	306002	1			T22	2		T1	47		T11	1394
bins_for_gpio_bits[3]	auto[1]	auto[0]	306254	1			T22	2		T1	47		T11	1390
bins_for_gpio_bits[3]	auto[1]	auto[1]	6293204	1			T22	61		T23	581		T1	323
bins_for_gpio_bits[4]	auto[0]	auto[0]	9980385	1			T22	214		T23	646		T1	1526
bins_for_gpio_bits[4]	auto[0]	auto[1]	306947	1			T22	1		T1	55		T11	1346
bins_for_gpio_bits[4]	auto[1]	auto[0]	307204	1			T22	1		T1	55		T11	1342
bins_for_gpio_bits[4]	auto[1]	auto[1]	6293217	1			T22	68		T23	516		T1	390
bins_for_gpio_bits[5]	auto[0]	auto[0]	9995814	1			T22	207		T23	552		T1	1419
bins_for_gpio_bits[5]	auto[0]	auto[1]	306739	1			T22	3		T1	66		T11	1347
bins_for_gpio_bits[5]	auto[1]	auto[0]	306975	1			T22	3		T1	67		T11	1342
bins_for_gpio_bits[5]	auto[1]	auto[1]	6278225	1			T22	71		T23	610		T1	474
bins_for_gpio_bits[6]	auto[0]	auto[0]	9995137	1			T22	224		T23	569		T1	1549
bins_for_gpio_bits[6]	auto[0]	auto[1]	306732	1			T22	2		T1	56		T11	1397
bins_for_gpio_bits[6]	auto[1]	auto[0]	307011	1			T22	2		T1	56		T11	1392
bins_for_gpio_bits[6]	auto[1]	auto[1]	6278873	1			T22	56		T23	593		T1	365
bins_for_gpio_bits[7]	auto[0]	auto[0]	9996179	1			T22	221		T23	579		T1	1427
bins_for_gpio_bits[7]	auto[0]	auto[1]	306305	1			T22	4		T1	62		T11	1401
bins_for_gpio_bits[7]	auto[1]	auto[0]	306565	1			T22	4		T1	62		T11	1395
bins_for_gpio_bits[7]	auto[1]	auto[1]	6278704	1			T22	55		T23	583		T1	475
bins_for_gpio_bits[8]	auto[0]	auto[0]	10000509	1			T22	208		T23	633		T1	1525
bins_for_gpio_bits[8]	auto[0]	auto[1]	305930	1			T22	2		T1	58		T11	1394
bins_for_gpio_bits[8]	auto[1]	auto[0]	306213	1			T22	2		T1	59		T11	1391
bins_for_gpio_bits[8]	auto[1]	auto[1]	6275101	1			T22	72		T23	529		T1	384
bins_for_gpio_bits[9]	auto[0]	auto[0]	10004633	1			T22	217		T23	559		T1	1487
bins_for_gpio_bits[9]	auto[0]	auto[1]	306310	1			T22	3		T1	62		T11	1317
bins_for_gpio_bits[9]	auto[1]	auto[0]	306564	1			T22	3		T1	62		T11	1315
bins_for_gpio_bits[9]	auto[1]	auto[1]	6270246	1			T22	61		T23	603		T1	415
bins_for_gpio_bits[10]	auto[0]	auto[0]	10002564	1			T22	188		T23	554		T1	1453
bins_for_gpio_bits[10]	auto[0]	auto[1]	306377	1			T22	7		T1	66		T11	1391
bins_for_gpio_bits[10]	auto[1]	auto[0]	306627	1			T22	7		T1	66		T11	1388
bins_for_gpio_bits[10]	auto[1]	auto[1]	6272185	1			T22	82		T23	608		T1	441
bins_for_gpio_bits[11]	auto[0]	auto[0]	9987645	1			T22	200		T23	616		T1	1526
bins_for_gpio_bits[11]	auto[0]	auto[1]	306536	1			T22	6		T1	64		T11	1321
bins_for_gpio_bits[11]	auto[1]	auto[0]	306814	1			T22	6		T1	64		T11	1317
bins_for_gpio_bits[11]	auto[1]	auto[1]	6286758	1			T22	72		T23	546		T1	372
bins_for_gpio_bits[12]	auto[0]	auto[0]	10005291	1			T22	216		T23	646		T1	1432
bins_for_gpio_bits[12]	auto[0]	auto[1]	306202	1			T22	3		T1	63		T11	1380
bins_for_gpio_bits[12]	auto[1]	auto[0]	306446	1			T22	3		T1	63		T11	1376
bins_for_gpio_bits[12]	auto[1]	auto[1]	6269814	1			T22	62		T23	516		T1	468
bins_for_gpio_bits[13]	auto[0]	auto[0]	9994245	1			T22	216		T23	549		T1	1418
bins_for_gpio_bits[13]	auto[0]	auto[1]	306913	1			T22	2		T1	61		T11	1331
bins_for_gpio_bits[13]	auto[1]	auto[0]	307184	1			T22	2		T1	62		T11	1329
bins_for_gpio_bits[13]	auto[1]	auto[1]	6279411	1			T22	64		T23	613		T1	485
bins_for_gpio_bits[14]	auto[0]	auto[0]	10000166	1			T22	210		T23	567		T1	1600
bins_for_gpio_bits[14]	auto[0]	auto[1]	306544	1			T22	3		T1	44		T11	1346
bins_for_gpio_bits[14]	auto[1]	auto[0]	306828	1			T22	3		T1	44		T11	1340
bins_for_gpio_bits[14]	auto[1]	auto[1]	6274215	1			T22	68		T23	595		T1	338
bins_for_gpio_bits[15]	auto[0]	auto[0]	9993858	1			T22	220		T23	577		T1	1558
bins_for_gpio_bits[15]	auto[0]	auto[1]	307158	1			T22	3		T1	61		T11	1381
bins_for_gpio_bits[15]	auto[1]	auto[0]	307463	1			T22	3		T1	61		T11	1378
bins_for_gpio_bits[15]	auto[1]	auto[1]	6279274	1			T22	58		T23	585		T1	346
bins_for_gpio_bits[16]	auto[0]	auto[0]	9995054	1			T22	213		T23	607		T1	1453
bins_for_gpio_bits[16]	auto[0]	auto[1]	306879	1			T22	3		T1	66		T11	1354
bins_for_gpio_bits[16]	auto[1]	auto[0]	307188	1			T22	3		T1	66		T11	1347
bins_for_gpio_bits[16]	auto[1]	auto[1]	6278632	1			T22	65		T23	555		T1	441
bins_for_gpio_bits[17]	auto[0]	auto[0]	10004838	1			T22	213		T23	561		T1	1408
bins_for_gpio_bits[17]	auto[0]	auto[1]	306584	1			T22	3		T1	66		T11	1425
bins_for_gpio_bits[17]	auto[1]	auto[0]	306845	1			T22	3		T1	66		T11	1423
bins_for_gpio_bits[17]	auto[1]	auto[1]	6269486	1			T22	65		T23	601		T1	486
bins_for_gpio_bits[18]	auto[0]	auto[0]	10010545	1			T22	213		T23	601		T1	1448
bins_for_gpio_bits[18]	auto[0]	auto[1]	306575	1			T22	4		T1	61		T11	1352
bins_for_gpio_bits[18]	auto[1]	auto[0]	306860	1			T22	4		T1	61		T11	1350
bins_for_gpio_bits[18]	auto[1]	auto[1]	6263773	1			T22	63		T23	561		T1	456
bins_for_gpio_bits[19]	auto[0]	auto[0]	10006468	1			T22	217		T23	488		T1	1530
bins_for_gpio_bits[19]	auto[0]	auto[1]	306284	1			T22	3		T1	56		T11	1376
bins_for_gpio_bits[19]	auto[1]	auto[0]	306559	1			T22	3		T1	56		T11	1375
bins_for_gpio_bits[19]	auto[1]	auto[1]	6268442	1			T22	61		T23	674		T1	384
bins_for_gpio_bits[20]	auto[0]	auto[0]	10011482	1			T22	202		T23	604		T1	1530
bins_for_gpio_bits[20]	auto[0]	auto[1]	305893	1			T22	4		T1	48		T11	1344
bins_for_gpio_bits[20]	auto[1]	auto[0]	306204	1			T22	4		T1	48		T11	1340
bins_for_gpio_bits[20]	auto[1]	auto[1]	6264174	1			T22	74		T23	558		T1	400
bins_for_gpio_bits[21]	auto[0]	auto[0]	10012741	1			T22	197		T23	557		T1	1434
bins_for_gpio_bits[21]	auto[0]	auto[1]	306362	1			T22	5		T1	60		T11	1382
bins_for_gpio_bits[21]	auto[1]	auto[0]	306678	1			T22	5		T1	60		T11	1380
bins_for_gpio_bits[21]	auto[1]	auto[1]	6261972	1			T22	77		T23	605		T1	472
bins_for_gpio_bits[22]	auto[0]	auto[0]	9994975	1			T22	202		T23	615		T1	1591
bins_for_gpio_bits[22]	auto[0]	auto[1]	306487	1			T22	5		T1	56		T11	1348
bins_for_gpio_bits[22]	auto[1]	auto[0]	306794	1			T22	5		T1	56		T11	1346
bins_for_gpio_bits[22]	auto[1]	auto[1]	6279497	1			T22	72		T23	547		T1	323
bins_for_gpio_bits[23]	auto[0]	auto[0]	10014890	1			T22	206		T23	523		T1	1509
bins_for_gpio_bits[23]	auto[0]	auto[1]	306789	1			T22	2		T1	51		T11	1421
bins_for_gpio_bits[23]	auto[1]	auto[0]	307028	1			T22	2		T1	51		T11	1415
bins_for_gpio_bits[23]	auto[1]	auto[1]	6259046	1			T22	74		T23	639		T1	415
bins_for_gpio_bits[24]	auto[0]	auto[0]	10011217	1			T22	219		T23	676		T1	1435
bins_for_gpio_bits[24]	auto[0]	auto[1]	306612	1			T22	1		T1	65		T11	1316
bins_for_gpio_bits[24]	auto[1]	auto[0]	306899	1			T22	1		T1	65		T11	1315
bins_for_gpio_bits[24]	auto[1]	auto[1]	6263025	1			T22	63		T23	486		T1	461
bins_for_gpio_bits[25]	auto[0]	auto[0]	10005163	1			T22	219		T23	605		T1	1498
bins_for_gpio_bits[25]	auto[0]	auto[1]	306197	1			T22	3		T1	49		T11	1347
bins_for_gpio_bits[25]	auto[1]	auto[0]	306488	1			T22	3		T1	50		T11	1342
bins_for_gpio_bits[25]	auto[1]	auto[1]	6269905	1			T22	59		T23	557		T1	429
bins_for_gpio_bits[26]	auto[0]	auto[0]	9997366	1			T22	200		T23	640		T1	1629
bins_for_gpio_bits[26]	auto[0]	auto[1]	306665	1			T22	7		T1	39		T11	1399
bins_for_gpio_bits[26]	auto[1]	auto[0]	306923	1			T22	7		T1	40		T11	1396
bins_for_gpio_bits[26]	auto[1]	auto[1]	6276799	1			T22	70		T23	522		T1	318
bins_for_gpio_bits[27]	auto[0]	auto[0]	10010097	1			T22	219		T23	597		T1	1451
bins_for_gpio_bits[27]	auto[0]	auto[1]	306724	1			T22	3		T1	55		T11	1412
bins_for_gpio_bits[27]	auto[1]	auto[0]	306949	1			T22	3		T1	55		T11	1403
bins_for_gpio_bits[27]	auto[1]	auto[1]	6263983	1			T22	59		T23	565		T1	465
bins_for_gpio_bits[28]	auto[0]	auto[0]	10002120	1			T22	218		T23	633		T1	1485
bins_for_gpio_bits[28]	auto[0]	auto[1]	306388	1			T22	5		T1	60		T11	1372
bins_for_gpio_bits[28]	auto[1]	auto[0]	306672	1			T22	5		T1	60		T11	1367
bins_for_gpio_bits[28]	auto[1]	auto[1]	6272573	1			T22	56		T23	529		T1	421
bins_for_gpio_bits[29]	auto[0]	auto[0]	10010802	1			T22	208		T23	563		T1	1420
bins_for_gpio_bits[29]	auto[0]	auto[1]	305389	1			T22	7		T1	61		T11	1267
bins_for_gpio_bits[29]	auto[1]	auto[0]	305641	1			T22	7		T1	62		T11	1263
bins_for_gpio_bits[29]	auto[1]	auto[1]	6265921	1			T22	62		T23	599		T1	483
bins_for_gpio_bits[30]	auto[0]	auto[0]	10007465	1			T22	211		T23	627		T1	1546
bins_for_gpio_bits[30]	auto[0]	auto[1]	306659	1			T22	4		T1	51		T11	1358
bins_for_gpio_bits[30]	auto[1]	auto[0]	306946	1			T22	4		T1	51		T11	1353
bins_for_gpio_bits[30]	auto[1]	auto[1]	6266683	1			T22	65		T23	535		T1	378
bins_for_gpio_bits[31]	auto[0]	auto[0]	10010469	1			T22	223		T23	697		T1	1441
bins_for_gpio_bits[31]	auto[0]	auto[1]	306256	1			T22	1		T1	62		T11	1365
bins_for_gpio_bits[31]	auto[1]	auto[0]	306548	1			T22	1		T1	62		T11	1359
bins_for_gpio_bits[31]	auto[1]	auto[1]	6264480	1			T22	59		T23	465		T1	461