Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9632943 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1196 |
| auto[1] |
7568291 |
1 |
|
|
T1 |
924 |
|
T11 |
29302 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16235025 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2075 |
| auto[1] |
966209 |
1 |
|
|
T1 |
45 |
|
T11 |
3467 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9643686 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1068 |
| auto[1] |
7557548 |
1 |
|
|
T1 |
1052 |
|
T11 |
28318 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3298251 |
1 |
|
|
T1 |
532 |
|
T11 |
12638 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
482255 |
1 |
|
|
T1 |
19 |
|
T11 |
1723 |
|
T18 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3293088 |
1 |
|
|
T1 |
475 |
|
T11 |
12213 |
|
T2 |
12 |
| auto[1] |
auto[1] |
auto[1] |
483954 |
1 |
|
|
T1 |
26 |
|
T11 |
1744 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9616046 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1035 |
| auto[1] |
7585188 |
1 |
|
|
T1 |
1085 |
|
T11 |
28836 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16231559 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2073 |
| auto[1] |
969675 |
1 |
|
|
T1 |
47 |
|
T11 |
3429 |
|
T2 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9622274 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1224 |
| auto[1] |
7578960 |
1 |
|
|
T1 |
896 |
|
T11 |
27914 |
|
T2 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3297037 |
1 |
|
|
T1 |
419 |
|
T11 |
11849 |
|
T2 |
19 |
| auto[1] |
auto[0] |
auto[1] |
482485 |
1 |
|
|
T1 |
19 |
|
T11 |
1640 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3312248 |
1 |
|
|
T1 |
430 |
|
T11 |
12636 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[1] |
487190 |
1 |
|
|
T1 |
28 |
|
T11 |
1789 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9661104 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1112 |
| auto[1] |
7540130 |
1 |
|
|
T1 |
1008 |
|
T11 |
29151 |
|
T2 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16236879 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
964355 |
1 |
|
|
T1 |
39 |
|
T11 |
3326 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9659116 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1239 |
| auto[1] |
7542118 |
1 |
|
|
T1 |
881 |
|
T11 |
27794 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3301528 |
1 |
|
|
T1 |
464 |
|
T11 |
11135 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
484281 |
1 |
|
|
T1 |
21 |
|
T11 |
1495 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3276235 |
1 |
|
|
T1 |
378 |
|
T11 |
13333 |
|
T2 |
9 |
| auto[1] |
auto[1] |
auto[1] |
480074 |
1 |
|
|
T1 |
18 |
|
T11 |
1831 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9604688 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
993 |
| auto[1] |
7596546 |
1 |
|
|
T1 |
1127 |
|
T11 |
27405 |
|
T2 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16227952 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2079 |
| auto[1] |
973282 |
1 |
|
|
T1 |
41 |
|
T11 |
3423 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9591631 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1024 |
| auto[1] |
7609603 |
1 |
|
|
T1 |
1096 |
|
T11 |
28664 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3297631 |
1 |
|
|
T1 |
526 |
|
T11 |
13503 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
481831 |
1 |
|
|
T1 |
28 |
|
T11 |
1821 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3338690 |
1 |
|
|
T1 |
529 |
|
T11 |
11738 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[1] |
491451 |
1 |
|
|
T1 |
13 |
|
T11 |
1602 |
|
T18 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9610010 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1030 |
| auto[1] |
7591224 |
1 |
|
|
T1 |
1090 |
|
T11 |
31187 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16237232 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
964002 |
1 |
|
|
T1 |
39 |
|
T11 |
3493 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9656299 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1036 |
| auto[1] |
7544935 |
1 |
|
|
T1 |
1084 |
|
T11 |
29004 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3288984 |
1 |
|
|
T1 |
535 |
|
T11 |
12358 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
481410 |
1 |
|
|
T1 |
16 |
|
T11 |
1715 |
|
T18 |
17 |
| auto[1] |
auto[1] |
auto[0] |
3291949 |
1 |
|
|
T1 |
510 |
|
T11 |
13153 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
482592 |
1 |
|
|
T1 |
23 |
|
T11 |
1778 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9601069 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1105 |
| auto[1] |
7600165 |
1 |
|
|
T1 |
1015 |
|
T11 |
29142 |
|
T2 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16235230 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
966004 |
1 |
|
|
T1 |
39 |
|
T11 |
3460 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9639884 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
992 |
| auto[1] |
7561350 |
1 |
|
|
T1 |
1128 |
|
T11 |
29139 |
|
T2 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3285762 |
1 |
|
|
T1 |
543 |
|
T11 |
13284 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
480940 |
1 |
|
|
T1 |
25 |
|
T11 |
1913 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3309584 |
1 |
|
|
T1 |
546 |
|
T11 |
12395 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
485064 |
1 |
|
|
T1 |
14 |
|
T11 |
1547 |
|
T18 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9630354 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
852 |
| auto[1] |
7570880 |
1 |
|
|
T1 |
1268 |
|
T11 |
28865 |
|
T2 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16232290 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2087 |
| auto[1] |
968944 |
1 |
|
|
T1 |
33 |
|
T11 |
3770 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9621311 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1217 |
| auto[1] |
7579923 |
1 |
|
|
T1 |
903 |
|
T11 |
30310 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3318960 |
1 |
|
|
T1 |
344 |
|
T11 |
13745 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
486800 |
1 |
|
|
T1 |
15 |
|
T11 |
1994 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3292019 |
1 |
|
|
T1 |
526 |
|
T11 |
12795 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
482144 |
1 |
|
|
T1 |
18 |
|
T11 |
1776 |
|
T18 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9637380 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1061 |
| auto[1] |
7563854 |
1 |
|
|
T1 |
1059 |
|
T11 |
28546 |
|
T2 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16239489 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2079 |
| auto[1] |
961745 |
1 |
|
|
T1 |
41 |
|
T11 |
3655 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9676287 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1029 |
| auto[1] |
7524947 |
1 |
|
|
T1 |
1091 |
|
T11 |
29954 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3289609 |
1 |
|
|
T1 |
539 |
|
T11 |
13837 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
481792 |
1 |
|
|
T1 |
18 |
|
T11 |
1869 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3273593 |
1 |
|
|
T1 |
511 |
|
T11 |
12462 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[1] |
479953 |
1 |
|
|
T1 |
23 |
|
T11 |
1786 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9646436 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1137 |
| auto[1] |
7554798 |
1 |
|
|
T1 |
983 |
|
T11 |
28997 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16232545 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2078 |
| auto[1] |
968689 |
1 |
|
|
T1 |
42 |
|
T11 |
3662 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9630152 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1104 |
| auto[1] |
7571082 |
1 |
|
|
T1 |
1016 |
|
T11 |
29226 |
|
T2 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3299851 |
1 |
|
|
T1 |
488 |
|
T11 |
12863 |
|
T2 |
8 |
| auto[1] |
auto[0] |
auto[1] |
483813 |
1 |
|
|
T1 |
16 |
|
T11 |
1882 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3302542 |
1 |
|
|
T1 |
486 |
|
T11 |
12701 |
|
T16 |
20 |
| auto[1] |
auto[1] |
auto[1] |
484876 |
1 |
|
|
T1 |
26 |
|
T11 |
1780 |
|
T18 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652916 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1010 |
| auto[1] |
7548318 |
1 |
|
|
T1 |
1110 |
|
T11 |
30118 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16238613 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2087 |
| auto[1] |
962621 |
1 |
|
|
T1 |
33 |
|
T11 |
3573 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9664222 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1323 |
| auto[1] |
7537012 |
1 |
|
|
T1 |
797 |
|
T11 |
29828 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3299211 |
1 |
|
|
T1 |
383 |
|
T11 |
12820 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
483502 |
1 |
|
|
T1 |
22 |
|
T11 |
1690 |
|
T18 |
16 |
| auto[1] |
auto[1] |
auto[0] |
3275180 |
1 |
|
|
T1 |
381 |
|
T11 |
13435 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
479119 |
1 |
|
|
T1 |
11 |
|
T11 |
1883 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638520 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1012 |
| auto[1] |
7562714 |
1 |
|
|
T1 |
1108 |
|
T11 |
28249 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16235868 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2078 |
| auto[1] |
965366 |
1 |
|
|
T1 |
42 |
|
T11 |
3673 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9655227 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1116 |
| auto[1] |
7546007 |
1 |
|
|
T1 |
1004 |
|
T11 |
30064 |
|
T2 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3299850 |
1 |
|
|
T1 |
508 |
|
T11 |
13469 |
|
T2 |
12 |
| auto[1] |
auto[0] |
auto[1] |
484806 |
1 |
|
|
T1 |
22 |
|
T11 |
1899 |
|
T18 |
11 |
| auto[1] |
auto[1] |
auto[0] |
3280791 |
1 |
|
|
T1 |
454 |
|
T11 |
12922 |
|
T2 |
19 |
| auto[1] |
auto[1] |
auto[1] |
480560 |
1 |
|
|
T1 |
20 |
|
T11 |
1774 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9654372 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1017 |
| auto[1] |
7546862 |
1 |
|
|
T1 |
1103 |
|
T11 |
29752 |
|
T2 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16231669 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2089 |
| auto[1] |
969565 |
1 |
|
|
T1 |
31 |
|
T11 |
3652 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9621933 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1243 |
| auto[1] |
7579301 |
1 |
|
|
T1 |
877 |
|
T11 |
29649 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3338072 |
1 |
|
|
T1 |
413 |
|
T11 |
12406 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
491021 |
1 |
|
|
T1 |
18 |
|
T11 |
1706 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3271664 |
1 |
|
|
T1 |
433 |
|
T11 |
13591 |
|
T2 |
17 |
| auto[1] |
auto[1] |
auto[1] |
478544 |
1 |
|
|
T1 |
13 |
|
T11 |
1946 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629265 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
915 |
| auto[1] |
7571969 |
1 |
|
|
T1 |
1205 |
|
T11 |
27275 |
|
T2 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16234149 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2083 |
| auto[1] |
967085 |
1 |
|
|
T1 |
37 |
|
T11 |
3652 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638705 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1137 |
| auto[1] |
7562529 |
1 |
|
|
T1 |
983 |
|
T11 |
30420 |
|
T2 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3294466 |
1 |
|
|
T1 |
395 |
|
T11 |
13851 |
|
T2 |
18 |
| auto[1] |
auto[0] |
auto[1] |
483034 |
1 |
|
|
T1 |
21 |
|
T11 |
1899 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3300978 |
1 |
|
|
T1 |
551 |
|
T11 |
12917 |
|
T16 |
9 |
| auto[1] |
auto[1] |
auto[1] |
484051 |
1 |
|
|
T1 |
16 |
|
T11 |
1753 |
|
T18 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9606647 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1116 |
| auto[1] |
7594587 |
1 |
|
|
T1 |
1004 |
|
T11 |
28949 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16233906 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2083 |
| auto[1] |
967328 |
1 |
|
|
T1 |
37 |
|
T11 |
3329 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9634870 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1017 |
| auto[1] |
7566364 |
1 |
|
|
T1 |
1103 |
|
T11 |
27548 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3281966 |
1 |
|
|
T1 |
507 |
|
T11 |
12218 |
|
T2 |
27 |
| auto[1] |
auto[0] |
auto[1] |
480650 |
1 |
|
|
T1 |
21 |
|
T11 |
1688 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3317070 |
1 |
|
|
T1 |
559 |
|
T11 |
12001 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
486678 |
1 |
|
|
T1 |
16 |
|
T11 |
1641 |
|
T18 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9641199 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1209 |
| auto[1] |
7560035 |
1 |
|
|
T1 |
911 |
|
T11 |
29542 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16240585 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2079 |
| auto[1] |
960649 |
1 |
|
|
T1 |
41 |
|
T11 |
3704 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9679027 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1118 |
| auto[1] |
7522207 |
1 |
|
|
T1 |
1002 |
|
T11 |
30124 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3284994 |
1 |
|
|
T1 |
528 |
|
T11 |
13088 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
480833 |
1 |
|
|
T1 |
25 |
|
T11 |
1804 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3276564 |
1 |
|
|
T1 |
433 |
|
T11 |
13332 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
479816 |
1 |
|
|
T1 |
16 |
|
T11 |
1900 |
|
T18 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638564 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
978 |
| auto[1] |
7562670 |
1 |
|
|
T1 |
1142 |
|
T11 |
27351 |
|
T2 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16235119 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2079 |
| auto[1] |
966115 |
1 |
|
|
T1 |
41 |
|
T11 |
3737 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9631628 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1006 |
| auto[1] |
7569606 |
1 |
|
|
T1 |
1114 |
|
T11 |
30546 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3322307 |
1 |
|
|
T1 |
515 |
|
T11 |
14199 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
486640 |
1 |
|
|
T1 |
15 |
|
T11 |
1991 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3281184 |
1 |
|
|
T1 |
558 |
|
T11 |
12610 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[1] |
479475 |
1 |
|
|
T1 |
26 |
|
T11 |
1746 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9635537 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
857 |
| auto[1] |
7565697 |
1 |
|
|
T1 |
1263 |
|
T11 |
26906 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16240317 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2088 |
| auto[1] |
960917 |
1 |
|
|
T1 |
32 |
|
T11 |
3555 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9669962 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1177 |
| auto[1] |
7531272 |
1 |
|
|
T1 |
943 |
|
T11 |
29353 |
|
T2 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3295901 |
1 |
|
|
T1 |
391 |
|
T11 |
13748 |
|
T2 |
6 |
| auto[1] |
auto[0] |
auto[1] |
480497 |
1 |
|
|
T1 |
9 |
|
T11 |
1950 |
|
T18 |
17 |
| auto[1] |
auto[1] |
auto[0] |
3274454 |
1 |
|
|
T1 |
520 |
|
T11 |
12050 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[1] |
480420 |
1 |
|
|
T1 |
23 |
|
T11 |
1605 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9656051 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1083 |
| auto[1] |
7545183 |
1 |
|
|
T1 |
1037 |
|
T11 |
28357 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16228680 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2076 |
| auto[1] |
972554 |
1 |
|
|
T1 |
44 |
|
T11 |
3492 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9601204 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1013 |
| auto[1] |
7600030 |
1 |
|
|
T1 |
1107 |
|
T11 |
29551 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3313966 |
1 |
|
|
T1 |
501 |
|
T11 |
12938 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
486993 |
1 |
|
|
T1 |
23 |
|
T11 |
1770 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3313510 |
1 |
|
|
T1 |
562 |
|
T11 |
13121 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
485561 |
1 |
|
|
T1 |
21 |
|
T11 |
1722 |
|
T18 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9673006 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
981 |
| auto[1] |
7528228 |
1 |
|
|
T1 |
1139 |
|
T11 |
28807 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16233857 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2085 |
| auto[1] |
967377 |
1 |
|
|
T1 |
35 |
|
T11 |
3589 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629681 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1143 |
| auto[1] |
7571553 |
1 |
|
|
T1 |
977 |
|
T11 |
29569 |
|
T2 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3308858 |
1 |
|
|
T1 |
455 |
|
T11 |
12895 |
|
T2 |
31 |
| auto[1] |
auto[0] |
auto[1] |
484955 |
1 |
|
|
T1 |
15 |
|
T11 |
1839 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3295318 |
1 |
|
|
T1 |
487 |
|
T11 |
13085 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[1] |
482422 |
1 |
|
|
T1 |
20 |
|
T11 |
1750 |
|
T18 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |