Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9634627 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
963 |
| auto[1] |
7566607 |
1 |
|
|
T1 |
1157 |
|
T11 |
28642 |
|
T2 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16232841 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2069 |
| auto[1] |
968393 |
1 |
|
|
T1 |
51 |
|
T11 |
3581 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9624909 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
984 |
| auto[1] |
7576325 |
1 |
|
|
T1 |
1136 |
|
T11 |
29737 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3299424 |
1 |
|
|
T1 |
465 |
|
T11 |
13188 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
482636 |
1 |
|
|
T1 |
24 |
|
T11 |
1687 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3308508 |
1 |
|
|
T1 |
620 |
|
T11 |
12968 |
|
T2 |
12 |
| auto[1] |
auto[1] |
auto[1] |
485757 |
1 |
|
|
T1 |
27 |
|
T11 |
1894 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |