Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9618673 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1244 |
| auto[1] |
7582561 |
1 |
|
|
T1 |
876 |
|
T11 |
29368 |
|
T2 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16237885 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
963349 |
1 |
|
|
T1 |
39 |
|
T11 |
3640 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9658650 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1060 |
| auto[1] |
7542584 |
1 |
|
|
T1 |
1060 |
|
T11 |
30112 |
|
T2 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3290243 |
1 |
|
|
T1 |
578 |
|
T11 |
12904 |
|
T2 |
18 |
| auto[1] |
auto[0] |
auto[1] |
482282 |
1 |
|
|
T1 |
23 |
|
T11 |
1827 |
|
T18 |
21 |
| auto[1] |
auto[1] |
auto[0] |
3288992 |
1 |
|
|
T1 |
443 |
|
T11 |
13568 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
481067 |
1 |
|
|
T1 |
16 |
|
T11 |
1813 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |