Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9647127 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
956 |
| auto[1] |
7554107 |
1 |
|
|
T1 |
1164 |
|
T11 |
29567 |
|
T2 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16234106 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
967128 |
1 |
|
|
T1 |
39 |
|
T11 |
3514 |
|
T18 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9619552 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1195 |
| auto[1] |
7581682 |
1 |
|
|
T1 |
925 |
|
T11 |
29140 |
|
T2 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3308199 |
1 |
|
|
T1 |
357 |
|
T11 |
12429 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
483188 |
1 |
|
|
T1 |
21 |
|
T11 |
1722 |
|
T18 |
22 |
| auto[1] |
auto[1] |
auto[0] |
3306355 |
1 |
|
|
T1 |
529 |
|
T11 |
13197 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
483940 |
1 |
|
|
T1 |
18 |
|
T11 |
1792 |
|
T18 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |