Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9654098 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1070 |
| auto[1] |
7547136 |
1 |
|
|
T1 |
1050 |
|
T11 |
27068 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16234580 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
966654 |
1 |
|
|
T1 |
39 |
|
T11 |
3370 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9631267 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1146 |
| auto[1] |
7569967 |
1 |
|
|
T1 |
974 |
|
T11 |
28240 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3300458 |
1 |
|
|
T1 |
479 |
|
T11 |
13378 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
484141 |
1 |
|
|
T1 |
17 |
|
T11 |
1901 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3302855 |
1 |
|
|
T1 |
456 |
|
T11 |
11492 |
|
T2 |
19 |
| auto[1] |
auto[1] |
auto[1] |
482513 |
1 |
|
|
T1 |
22 |
|
T11 |
1469 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |