Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9632943 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1196 |
| auto[1] |
7568291 |
1 |
|
|
T1 |
924 |
|
T11 |
29302 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14140388 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1838 |
| auto[1] |
3060846 |
1 |
|
|
T1 |
282 |
|
T11 |
18779 |
|
T12 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9614998 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1070 |
| auto[1] |
7586236 |
1 |
|
|
T1 |
1050 |
|
T11 |
29676 |
|
T12 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2259786 |
1 |
|
|
T1 |
398 |
|
T11 |
5295 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1528953 |
1 |
|
|
T1 |
178 |
|
T11 |
9303 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2265604 |
1 |
|
|
T1 |
370 |
|
T11 |
5602 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1531893 |
1 |
|
|
T1 |
104 |
|
T11 |
9476 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |