Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9616046 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1035 |
| auto[1] |
7585188 |
1 |
|
|
T1 |
1085 |
|
T11 |
28836 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14148028 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1827 |
| auto[1] |
3053206 |
1 |
|
|
T1 |
293 |
|
T11 |
18928 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626477 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1027 |
| auto[1] |
7574757 |
1 |
|
|
T1 |
1093 |
|
T11 |
30187 |
|
T12 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2245046 |
1 |
|
|
T1 |
394 |
|
T11 |
5821 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1518190 |
1 |
|
|
T1 |
141 |
|
T11 |
9601 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2276505 |
1 |
|
|
T1 |
406 |
|
T11 |
5438 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[1] |
1535016 |
1 |
|
|
T1 |
152 |
|
T11 |
9327 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |