Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9661104 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1112 |
| auto[1] |
7540130 |
1 |
|
|
T1 |
1008 |
|
T11 |
29151 |
|
T2 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14149157 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1932 |
| auto[1] |
3052077 |
1 |
|
|
T1 |
188 |
|
T11 |
19151 |
|
T12 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9648485 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1149 |
| auto[1] |
7552749 |
1 |
|
|
T1 |
971 |
|
T11 |
30434 |
|
T12 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2261747 |
1 |
|
|
T1 |
359 |
|
T11 |
5734 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1530725 |
1 |
|
|
T1 |
105 |
|
T11 |
9730 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2238925 |
1 |
|
|
T1 |
424 |
|
T11 |
5549 |
|
T16 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1521352 |
1 |
|
|
T1 |
83 |
|
T11 |
9421 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |