Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9604688 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
993 |
| auto[1] |
7596546 |
1 |
|
|
T1 |
1127 |
|
T11 |
27405 |
|
T2 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14136837 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1899 |
| auto[1] |
3064397 |
1 |
|
|
T1 |
221 |
|
T11 |
18917 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9608214 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1073 |
| auto[1] |
7593020 |
1 |
|
|
T1 |
1047 |
|
T11 |
29485 |
|
T12 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253001 |
1 |
|
|
T1 |
417 |
|
T11 |
5589 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1525894 |
1 |
|
|
T1 |
103 |
|
T11 |
9967 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2275622 |
1 |
|
|
T1 |
409 |
|
T11 |
4979 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1538503 |
1 |
|
|
T1 |
118 |
|
T11 |
8950 |
|
T18 |
134 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |