Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9610010 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1030 |
| auto[1] |
7591224 |
1 |
|
|
T1 |
1090 |
|
T11 |
31187 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14152442 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1857 |
| auto[1] |
3048792 |
1 |
|
|
T1 |
263 |
|
T11 |
18976 |
|
T2 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9650494 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1170 |
| auto[1] |
7550740 |
1 |
|
|
T1 |
950 |
|
T11 |
30566 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2261710 |
1 |
|
|
T1 |
355 |
|
T11 |
5526 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1526136 |
1 |
|
|
T1 |
125 |
|
T11 |
9272 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2240238 |
1 |
|
|
T1 |
332 |
|
T11 |
6064 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1522656 |
1 |
|
|
T1 |
138 |
|
T11 |
9704 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |