Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9647154 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
840 |
| auto[1] |
7554080 |
1 |
|
|
T1 |
1280 |
|
T11 |
29699 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16232904 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2088 |
| auto[1] |
968330 |
1 |
|
|
T1 |
32 |
|
T11 |
3958 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626732 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
878 |
| auto[1] |
7574502 |
1 |
|
|
T1 |
1242 |
|
T11 |
31708 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3300844 |
1 |
|
|
T1 |
467 |
|
T11 |
13598 |
|
T2 |
26 |
| auto[1] |
auto[0] |
auto[1] |
483082 |
1 |
|
|
T1 |
6 |
|
T11 |
1933 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3305328 |
1 |
|
|
T1 |
743 |
|
T11 |
14152 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
485248 |
1 |
|
|
T1 |
26 |
|
T11 |
2025 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |