Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9601069 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1105 |
| auto[1] |
7600165 |
1 |
|
|
T1 |
1015 |
|
T11 |
29142 |
|
T2 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14147111 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1844 |
| auto[1] |
3054123 |
1 |
|
|
T1 |
276 |
|
T11 |
17574 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9657173 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1158 |
| auto[1] |
7544061 |
1 |
|
|
T1 |
962 |
|
T11 |
28004 |
|
T12 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2230496 |
1 |
|
|
T1 |
347 |
|
T11 |
4842 |
|
T12 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1521072 |
1 |
|
|
T1 |
161 |
|
T11 |
7644 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2259442 |
1 |
|
|
T1 |
339 |
|
T11 |
5588 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1533051 |
1 |
|
|
T1 |
115 |
|
T11 |
9930 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |