Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9630354 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
852 |
| auto[1] |
7570880 |
1 |
|
|
T1 |
1268 |
|
T11 |
28865 |
|
T2 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14143376 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1887 |
| auto[1] |
3057858 |
1 |
|
|
T1 |
233 |
|
T11 |
17619 |
|
T2 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9620329 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
835 |
| auto[1] |
7580905 |
1 |
|
|
T1 |
1285 |
|
T11 |
28319 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2248920 |
1 |
|
|
T1 |
383 |
|
T11 |
5628 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1522586 |
1 |
|
|
T1 |
56 |
|
T11 |
8931 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2274127 |
1 |
|
|
T1 |
669 |
|
T11 |
5072 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1535272 |
1 |
|
|
T1 |
177 |
|
T11 |
8688 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |