Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9637380 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1061 |
| auto[1] |
7563854 |
1 |
|
|
T1 |
1059 |
|
T11 |
28546 |
|
T2 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14134024 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1922 |
| auto[1] |
3067210 |
1 |
|
|
T1 |
198 |
|
T11 |
18117 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9610862 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1144 |
| auto[1] |
7590372 |
1 |
|
|
T1 |
976 |
|
T11 |
29220 |
|
T12 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2261267 |
1 |
|
|
T1 |
417 |
|
T11 |
5636 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1532513 |
1 |
|
|
T1 |
96 |
|
T11 |
9754 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2261895 |
1 |
|
|
T1 |
361 |
|
T11 |
5467 |
|
T2 |
9 |
| auto[1] |
auto[1] |
auto[1] |
1534697 |
1 |
|
|
T1 |
102 |
|
T11 |
8363 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |