Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9646436 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1137 |
| auto[1] |
7554798 |
1 |
|
|
T1 |
983 |
|
T11 |
28997 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14136888 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1835 |
| auto[1] |
3064346 |
1 |
|
|
T1 |
285 |
|
T11 |
18948 |
|
T12 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9604001 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1008 |
| auto[1] |
7597233 |
1 |
|
|
T1 |
1112 |
|
T11 |
30194 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2275252 |
1 |
|
|
T1 |
429 |
|
T11 |
5428 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1536583 |
1 |
|
|
T1 |
139 |
|
T11 |
8853 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2257635 |
1 |
|
|
T1 |
398 |
|
T11 |
5818 |
|
T18 |
484 |
| auto[1] |
auto[1] |
auto[1] |
1527763 |
1 |
|
|
T1 |
146 |
|
T11 |
10095 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |