Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652916 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1010 |
| auto[1] |
7548318 |
1 |
|
|
T1 |
1110 |
|
T11 |
30118 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14142617 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1910 |
| auto[1] |
3058617 |
1 |
|
|
T1 |
210 |
|
T11 |
17963 |
|
T12 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9635681 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1285 |
| auto[1] |
7565553 |
1 |
|
|
T1 |
835 |
|
T11 |
28824 |
|
T12 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2266317 |
1 |
|
|
T1 |
331 |
|
T11 |
5243 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1535966 |
1 |
|
|
T1 |
111 |
|
T11 |
8774 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2240619 |
1 |
|
|
T1 |
294 |
|
T11 |
5618 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1522651 |
1 |
|
|
T1 |
99 |
|
T11 |
9189 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |