Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638520 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1012 |
| auto[1] |
7562714 |
1 |
|
|
T1 |
1108 |
|
T11 |
28249 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14148519 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1888 |
| auto[1] |
3052715 |
1 |
|
|
T1 |
232 |
|
T11 |
17534 |
|
T12 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9622528 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1137 |
| auto[1] |
7578706 |
1 |
|
|
T1 |
983 |
|
T11 |
28245 |
|
T12 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260564 |
1 |
|
|
T1 |
361 |
|
T11 |
5813 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1523594 |
1 |
|
|
T1 |
107 |
|
T11 |
9666 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2265427 |
1 |
|
|
T1 |
390 |
|
T11 |
4898 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1529121 |
1 |
|
|
T1 |
125 |
|
T11 |
7868 |
|
T12 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |