Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9654372 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1017 |
| auto[1] |
7546862 |
1 |
|
|
T1 |
1103 |
|
T11 |
29752 |
|
T2 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14146775 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1918 |
| auto[1] |
3054459 |
1 |
|
|
T1 |
202 |
|
T11 |
17298 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9634017 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1091 |
| auto[1] |
7567217 |
1 |
|
|
T1 |
1029 |
|
T11 |
27518 |
|
T12 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2268289 |
1 |
|
|
T1 |
401 |
|
T11 |
5210 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1538246 |
1 |
|
|
T1 |
77 |
|
T11 |
8681 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2244469 |
1 |
|
|
T1 |
426 |
|
T11 |
5010 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1516213 |
1 |
|
|
T1 |
125 |
|
T11 |
8617 |
|
T2 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |