Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629265 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
915 |
| auto[1] |
7571969 |
1 |
|
|
T1 |
1205 |
|
T11 |
27275 |
|
T2 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14150042 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1948 |
| auto[1] |
3051192 |
1 |
|
|
T1 |
172 |
|
T11 |
18166 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9652350 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1206 |
| auto[1] |
7548884 |
1 |
|
|
T1 |
914 |
|
T11 |
28870 |
|
T2 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2239790 |
1 |
|
|
T1 |
317 |
|
T11 |
5696 |
|
T16 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1518476 |
1 |
|
|
T1 |
100 |
|
T11 |
9146 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2257902 |
1 |
|
|
T1 |
425 |
|
T11 |
5008 |
|
T16 |
20 |
| auto[1] |
auto[1] |
auto[1] |
1532716 |
1 |
|
|
T1 |
72 |
|
T11 |
9020 |
|
T18 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |