Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9606647 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1116 |
| auto[1] |
7594587 |
1 |
|
|
T1 |
1004 |
|
T11 |
28949 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14158652 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1884 |
| auto[1] |
3042582 |
1 |
|
|
T1 |
236 |
|
T11 |
17682 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9657714 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
943 |
| auto[1] |
7543520 |
1 |
|
|
T1 |
1177 |
|
T11 |
27733 |
|
T12 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240661 |
1 |
|
|
T1 |
542 |
|
T11 |
4734 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1513497 |
1 |
|
|
T1 |
130 |
|
T11 |
8433 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2260277 |
1 |
|
|
T1 |
399 |
|
T11 |
5317 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1529085 |
1 |
|
|
T1 |
106 |
|
T11 |
9249 |
|
T18 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |