Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9641199 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1209 |
| auto[1] |
7560035 |
1 |
|
|
T1 |
911 |
|
T11 |
29542 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14151463 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1948 |
| auto[1] |
3049771 |
1 |
|
|
T1 |
172 |
|
T11 |
18763 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9654305 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1386 |
| auto[1] |
7546929 |
1 |
|
|
T1 |
734 |
|
T11 |
29852 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2259485 |
1 |
|
|
T1 |
323 |
|
T11 |
5409 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1533448 |
1 |
|
|
T1 |
115 |
|
T11 |
9687 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2237673 |
1 |
|
|
T1 |
239 |
|
T11 |
5680 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1516323 |
1 |
|
|
T1 |
57 |
|
T11 |
9076 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |