Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9622750 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1224 |
| auto[1] |
7578484 |
1 |
|
|
T1 |
896 |
|
T11 |
30487 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16230033 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2081 |
| auto[1] |
971201 |
1 |
|
|
T1 |
39 |
|
T11 |
3469 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9615390 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1078 |
| auto[1] |
7585844 |
1 |
|
|
T1 |
1042 |
|
T11 |
28879 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3295170 |
1 |
|
|
T1 |
584 |
|
T11 |
12280 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
482922 |
1 |
|
|
T1 |
20 |
|
T11 |
1671 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3319473 |
1 |
|
|
T1 |
419 |
|
T11 |
13130 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[1] |
488279 |
1 |
|
|
T1 |
19 |
|
T11 |
1798 |
|
T18 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |