Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638564 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
978 |
| auto[1] |
7562670 |
1 |
|
|
T1 |
1142 |
|
T11 |
27351 |
|
T2 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14138783 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1922 |
| auto[1] |
3062451 |
1 |
|
|
T1 |
198 |
|
T11 |
17763 |
|
T2 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9597771 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1090 |
| auto[1] |
7603463 |
1 |
|
|
T1 |
1030 |
|
T11 |
28451 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2278091 |
1 |
|
|
T1 |
384 |
|
T11 |
5535 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1530778 |
1 |
|
|
T1 |
83 |
|
T11 |
9033 |
|
T2 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2262921 |
1 |
|
|
T1 |
448 |
|
T11 |
5153 |
|
T2 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1531673 |
1 |
|
|
T1 |
115 |
|
T11 |
8730 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |