Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9635537 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
857 |
| auto[1] |
7565697 |
1 |
|
|
T1 |
1263 |
|
T11 |
26906 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14161392 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1869 |
| auto[1] |
3039842 |
1 |
|
|
T1 |
251 |
|
T11 |
19100 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9677746 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
904 |
| auto[1] |
7523488 |
1 |
|
|
T1 |
1216 |
|
T11 |
30345 |
|
T12 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2249681 |
1 |
|
|
T1 |
411 |
|
T11 |
6111 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1524411 |
1 |
|
|
T1 |
114 |
|
T11 |
10500 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2233965 |
1 |
|
|
T1 |
554 |
|
T11 |
5134 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1515431 |
1 |
|
|
T1 |
137 |
|
T11 |
8600 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |