Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9656051 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1083 |
| auto[1] |
7545183 |
1 |
|
|
T1 |
1037 |
|
T11 |
28357 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14135929 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1856 |
| auto[1] |
3065305 |
1 |
|
|
T1 |
264 |
|
T11 |
18810 |
|
T12 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9602906 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1235 |
| auto[1] |
7598328 |
1 |
|
|
T1 |
885 |
|
T11 |
30152 |
|
T12 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2272020 |
1 |
|
|
T1 |
320 |
|
T11 |
5805 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1539651 |
1 |
|
|
T1 |
172 |
|
T11 |
9705 |
|
T2 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2261003 |
1 |
|
|
T1 |
301 |
|
T11 |
5537 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1525654 |
1 |
|
|
T1 |
92 |
|
T11 |
9105 |
|
T12 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |