Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9604470 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1089 |
| auto[1] |
7596764 |
1 |
|
|
T1 |
1031 |
|
T11 |
30516 |
|
T2 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16238604 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2093 |
| auto[1] |
962630 |
1 |
|
|
T1 |
27 |
|
T11 |
3529 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9666736 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1268 |
| auto[1] |
7534498 |
1 |
|
|
T1 |
852 |
|
T11 |
29159 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3274569 |
1 |
|
|
T1 |
427 |
|
T11 |
12792 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
479093 |
1 |
|
|
T1 |
16 |
|
T11 |
1667 |
|
T18 |
19 |
| auto[1] |
auto[1] |
auto[0] |
3297299 |
1 |
|
|
T1 |
398 |
|
T11 |
12838 |
|
T2 |
31 |
| auto[1] |
auto[1] |
auto[1] |
483537 |
1 |
|
|
T1 |
11 |
|
T11 |
1862 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |