Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9636646 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1152 |
| auto[1] |
7564588 |
1 |
|
|
T1 |
968 |
|
T11 |
28932 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16227738 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2083 |
| auto[1] |
973496 |
1 |
|
|
T1 |
37 |
|
T11 |
3500 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9607313 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
984 |
| auto[1] |
7593921 |
1 |
|
|
T1 |
1136 |
|
T11 |
28488 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3319855 |
1 |
|
|
T1 |
645 |
|
T11 |
12273 |
|
T2 |
26 |
| auto[1] |
auto[0] |
auto[1] |
486934 |
1 |
|
|
T1 |
17 |
|
T11 |
1700 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3300570 |
1 |
|
|
T1 |
454 |
|
T11 |
12715 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
486562 |
1 |
|
|
T1 |
20 |
|
T11 |
1800 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |