Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9638785 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
1128 |
| auto[1] |
7562449 |
1 |
|
|
T1 |
992 |
|
T11 |
29446 |
|
T12 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16236968 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
2065 |
| auto[1] |
964266 |
1 |
|
|
T1 |
55 |
|
T11 |
3638 |
|
T2 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9647352 |
1 |
|
|
T22 |
156 |
|
T23 |
1162 |
|
T1 |
773 |
| auto[1] |
7553882 |
1 |
|
|
T1 |
1347 |
|
T11 |
29723 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3309690 |
1 |
|
|
T1 |
758 |
|
T11 |
13223 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
484746 |
1 |
|
|
T1 |
31 |
|
T11 |
1770 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3279926 |
1 |
|
|
T1 |
534 |
|
T11 |
12862 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[1] |
479520 |
1 |
|
|
T1 |
24 |
|
T11 |
1868 |
|
T18 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |