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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
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T761 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2327785576 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 107035948 ps
T762 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3334390561 Aug 06 04:32:04 PM PDT 24 Aug 06 04:32:05 PM PDT 24 25857405 ps
T763 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2029127921 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:08 PM PDT 24 44194395 ps
T764 /workspace/coverage/cover_reg_top/11.gpio_intr_test.512763883 Aug 06 04:32:12 PM PDT 24 Aug 06 04:32:12 PM PDT 24 24636092 ps
T37 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2433152745 Aug 06 04:32:04 PM PDT 24 Aug 06 04:32:05 PM PDT 24 541400262 ps
T765 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2849040359 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:36 PM PDT 24 12035120 ps
T89 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1617621471 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:35 PM PDT 24 14595022 ps
T766 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3296033635 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:09 PM PDT 24 13907453 ps
T767 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2409366456 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:40 PM PDT 24 13219370 ps
T768 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2524247115 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 15157965 ps
T769 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2794557193 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:34 PM PDT 24 50158582 ps
T97 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3422344008 Aug 06 04:32:05 PM PDT 24 Aug 06 04:32:06 PM PDT 24 373271802 ps
T98 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3408480600 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 39457436 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4076066028 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:08 PM PDT 24 14434459 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2243767826 Aug 06 04:31:34 PM PDT 24 Aug 06 04:31:35 PM PDT 24 37235512 ps
T771 /workspace/coverage/cover_reg_top/19.gpio_intr_test.144555365 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 42735509 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3253926677 Aug 06 04:31:32 PM PDT 24 Aug 06 04:31:34 PM PDT 24 58547513 ps
T773 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4107625708 Aug 06 04:32:03 PM PDT 24 Aug 06 04:32:04 PM PDT 24 802086724 ps
T774 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.446623098 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:37 PM PDT 24 619262870 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3393485244 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:07 PM PDT 24 145472337 ps
T99 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1958645091 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:34 PM PDT 24 126036312 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3531737510 Aug 06 04:31:36 PM PDT 24 Aug 06 04:31:36 PM PDT 24 35680754 ps
T777 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1251638322 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:36 PM PDT 24 18261089 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.242820212 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 99231662 ps
T779 /workspace/coverage/cover_reg_top/28.gpio_intr_test.4012488579 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 16120902 ps
T780 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3993841921 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:44 PM PDT 24 12996528 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.170453271 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:37 PM PDT 24 52037613 ps
T782 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1499525831 Aug 06 04:32:41 PM PDT 24 Aug 06 04:32:42 PM PDT 24 14469505 ps
T783 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3241331843 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:34 PM PDT 24 29752423 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.462859204 Aug 06 04:31:36 PM PDT 24 Aug 06 04:31:36 PM PDT 24 11499904 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4140956933 Aug 06 04:31:37 PM PDT 24 Aug 06 04:31:41 PM PDT 24 519356454 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_intr_test.183766298 Aug 06 04:31:39 PM PDT 24 Aug 06 04:31:40 PM PDT 24 68723947 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3089687417 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:37 PM PDT 24 189688242 ps
T788 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3946479156 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 27697936 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2966301327 Aug 06 04:31:37 PM PDT 24 Aug 06 04:31:38 PM PDT 24 112540961 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2658749709 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 84438785 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1372735943 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:37 PM PDT 24 48843646 ps
T91 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3179128839 Aug 06 04:31:32 PM PDT 24 Aug 06 04:31:33 PM PDT 24 67551568 ps
T100 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4096299991 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 63476526 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1429699361 Aug 06 04:31:34 PM PDT 24 Aug 06 04:31:35 PM PDT 24 54357638 ps
T793 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.663715058 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 44112830 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1834615963 Aug 06 04:32:03 PM PDT 24 Aug 06 04:32:04 PM PDT 24 11976324 ps
T795 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1798276119 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 19083165 ps
T796 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2150896612 Aug 06 04:31:34 PM PDT 24 Aug 06 04:31:36 PM PDT 24 746463181 ps
T797 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.62598370 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:10 PM PDT 24 172265580 ps
T798 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3602530847 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 35110999 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.748661770 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:34 PM PDT 24 174137021 ps
T800 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.996594511 Aug 06 04:32:37 PM PDT 24 Aug 06 04:32:38 PM PDT 24 129404602 ps
T801 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1317186892 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 15600130 ps
T802 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1060844058 Aug 06 04:32:05 PM PDT 24 Aug 06 04:32:07 PM PDT 24 368875343 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2288957578 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:10 PM PDT 24 91787763 ps
T804 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2541990776 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:37 PM PDT 24 20709485 ps
T113 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4252805085 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:44 PM PDT 24 99439809 ps
T805 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4059553519 Aug 06 04:32:32 PM PDT 24 Aug 06 04:32:33 PM PDT 24 29867255 ps
T806 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2516607482 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:34 PM PDT 24 82184353 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1575736402 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:10 PM PDT 24 173533798 ps
T808 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2463447183 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:37 PM PDT 24 136339953 ps
T809 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3475107270 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 27059320 ps
T810 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.160597600 Aug 06 04:31:33 PM PDT 24 Aug 06 04:31:34 PM PDT 24 412040355 ps
T811 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1124364184 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:10 PM PDT 24 113276531 ps
T812 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2044924899 Aug 06 04:32:10 PM PDT 24 Aug 06 04:32:11 PM PDT 24 14598377 ps
T813 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.935037291 Aug 06 04:32:03 PM PDT 24 Aug 06 04:32:04 PM PDT 24 47602969 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3218031893 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:33 PM PDT 24 29200923 ps
T815 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2812117483 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 17805429 ps
T816 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4147480412 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 131319774 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_intr_test.113675809 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:36 PM PDT 24 17190067 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1665602159 Aug 06 04:31:32 PM PDT 24 Aug 06 04:31:33 PM PDT 24 114866272 ps
T819 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1538950693 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:10 PM PDT 24 20726347 ps
T820 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2220937396 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:07 PM PDT 24 27099500 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.533300860 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 14826500 ps
T822 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3756111009 Aug 06 04:32:03 PM PDT 24 Aug 06 04:32:04 PM PDT 24 75765075 ps
T823 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1410334192 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:41 PM PDT 24 209573536 ps
T824 /workspace/coverage/cover_reg_top/44.gpio_intr_test.438757041 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 85011003 ps
T825 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3365354188 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 48295441 ps
T826 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3193401542 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 38825032 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1778965892 Aug 06 04:32:38 PM PDT 24 Aug 06 04:32:40 PM PDT 24 53158208 ps
T828 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3195137441 Aug 06 04:32:06 PM PDT 24 Aug 06 04:32:06 PM PDT 24 83808403 ps
T829 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3695927812 Aug 06 04:32:38 PM PDT 24 Aug 06 04:32:39 PM PDT 24 34591291 ps
T830 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4042756955 Aug 06 04:31:34 PM PDT 24 Aug 06 04:31:35 PM PDT 24 35199229 ps
T831 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2355316163 Aug 06 04:32:09 PM PDT 24 Aug 06 04:32:10 PM PDT 24 62545776 ps
T832 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3323684287 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 55083092 ps
T833 /workspace/coverage/cover_reg_top/45.gpio_intr_test.757005914 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 12676550 ps
T834 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3110766345 Aug 06 04:32:33 PM PDT 24 Aug 06 04:32:34 PM PDT 24 26082393 ps
T835 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.560246805 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 23197111 ps
T836 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2644750207 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:08 PM PDT 24 12184468 ps
T837 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2609873974 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:35 PM PDT 24 11739500 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.514867155 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 1164638736 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1716438541 Aug 06 04:32:04 PM PDT 24 Aug 06 04:32:05 PM PDT 24 23295293 ps
T840 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3511661950 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:08 PM PDT 24 78458046 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3724251601 Aug 06 04:31:40 PM PDT 24 Aug 06 04:31:41 PM PDT 24 19401433 ps
T841 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1770935473 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 44068623 ps
T842 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.342405099 Aug 06 04:32:07 PM PDT 24 Aug 06 04:32:09 PM PDT 24 221981501 ps
T843 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1305224354 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 72513911 ps
T844 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1442009132 Aug 06 04:31:40 PM PDT 24 Aug 06 04:31:41 PM PDT 24 196903040 ps
T845 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.657292832 Aug 06 04:32:08 PM PDT 24 Aug 06 04:32:09 PM PDT 24 29513486 ps
T846 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.43299054 Aug 06 04:32:06 PM PDT 24 Aug 06 04:32:07 PM PDT 24 77727604 ps
T847 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2287545743 Aug 06 04:32:34 PM PDT 24 Aug 06 04:32:35 PM PDT 24 33695344 ps
T848 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.719354735 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 582894722 ps
T849 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1351754202 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 91404058 ps
T850 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.614532475 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 80778522 ps
T851 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4051645108 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 99037654 ps
T852 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2877312008 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:44 PM PDT 24 115597971 ps
T853 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050769748 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:38 PM PDT 24 235432585 ps
T854 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1145274275 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:43 PM PDT 24 149134171 ps
T855 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1526878341 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 24822939 ps
T856 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.273206944 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 18890346 ps
T857 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3963258443 Aug 06 04:33:02 PM PDT 24 Aug 06 04:33:04 PM PDT 24 361560318 ps
T858 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642722602 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 148814813 ps
T859 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.332112020 Aug 06 04:32:35 PM PDT 24 Aug 06 04:32:36 PM PDT 24 37483804 ps
T860 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3386044618 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 234619227 ps
T861 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3384969210 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 54045766 ps
T862 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3710813927 Aug 06 04:33:13 PM PDT 24 Aug 06 04:33:14 PM PDT 24 469037417 ps
T863 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2724674385 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:41 PM PDT 24 381199165 ps
T864 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840438485 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 38188644 ps
T865 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.755953578 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:07 PM PDT 24 71390220 ps
T866 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2008197488 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 225927446 ps
T867 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.280054079 Aug 06 04:33:03 PM PDT 24 Aug 06 04:33:04 PM PDT 24 67496269 ps
T868 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2244822729 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 193196304 ps
T869 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1845181304 Aug 06 04:32:37 PM PDT 24 Aug 06 04:32:39 PM PDT 24 89546435 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1655358637 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 66315906 ps
T871 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.661602851 Aug 06 04:33:02 PM PDT 24 Aug 06 04:33:04 PM PDT 24 581802718 ps
T872 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054628998 Aug 06 04:32:46 PM PDT 24 Aug 06 04:32:47 PM PDT 24 148725238 ps
T873 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.829502405 Aug 06 04:33:12 PM PDT 24 Aug 06 04:33:14 PM PDT 24 30204791 ps
T874 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1477577519 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:37 PM PDT 24 17751310 ps
T875 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1489706888 Aug 06 04:33:06 PM PDT 24 Aug 06 04:33:08 PM PDT 24 770118404 ps
T876 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2106253032 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:44 PM PDT 24 281685489 ps
T877 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1608426723 Aug 06 04:33:01 PM PDT 24 Aug 06 04:33:02 PM PDT 24 250935688 ps
T878 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.81347607 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:45 PM PDT 24 90789001 ps
T879 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1866446393 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 180749759 ps
T880 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1958282369 Aug 06 04:33:03 PM PDT 24 Aug 06 04:33:04 PM PDT 24 261590555 ps
T881 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1774407086 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 68877097 ps
T882 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805646047 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:08 PM PDT 24 49881023 ps
T883 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3917940247 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 309656155 ps
T884 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905456144 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 181581174 ps
T885 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1287806539 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:42 PM PDT 24 63577849 ps
T886 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2111508236 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 264940068 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1110502778 Aug 06 04:32:45 PM PDT 24 Aug 06 04:32:46 PM PDT 24 90396833 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1997381065 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 43743103 ps
T889 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3510197590 Aug 06 04:32:41 PM PDT 24 Aug 06 04:32:42 PM PDT 24 71196310 ps
T890 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1317616370 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:42 PM PDT 24 231385260 ps
T891 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855805972 Aug 06 04:32:46 PM PDT 24 Aug 06 04:32:47 PM PDT 24 57208670 ps
T892 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2662226257 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:45 PM PDT 24 143832721 ps
T893 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049670441 Aug 06 04:33:03 PM PDT 24 Aug 06 04:33:04 PM PDT 24 162975896 ps
T894 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.227106771 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:41 PM PDT 24 199626400 ps
T895 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1649279713 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 84976440 ps
T896 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.739825479 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 26882904 ps
T897 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844591822 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 411399035 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2015195745 Aug 06 04:33:06 PM PDT 24 Aug 06 04:33:07 PM PDT 24 414855502 ps
T899 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1948496717 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 370969986 ps
T900 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3613880165 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:41 PM PDT 24 146022951 ps
T901 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1049666775 Aug 06 04:32:46 PM PDT 24 Aug 06 04:32:47 PM PDT 24 100804750 ps
T902 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2073788760 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:39 PM PDT 24 131333239 ps
T903 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2288088622 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 145858337 ps
T904 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.899063381 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:43 PM PDT 24 199565246 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1671748205 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:43 PM PDT 24 54334116 ps
T906 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.206223456 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:09 PM PDT 24 277593772 ps
T907 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.285431424 Aug 06 04:33:09 PM PDT 24 Aug 06 04:33:10 PM PDT 24 64387941 ps
T908 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3724371889 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 142977082 ps
T909 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.65633467 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 44998872 ps
T910 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181606662 Aug 06 04:33:00 PM PDT 24 Aug 06 04:33:02 PM PDT 24 194698891 ps
T911 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2071634177 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:09 PM PDT 24 275085586 ps
T912 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1703056061 Aug 06 04:33:10 PM PDT 24 Aug 06 04:33:11 PM PDT 24 70068856 ps
T913 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887820127 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:37 PM PDT 24 277350139 ps
T914 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191863424 Aug 06 04:32:41 PM PDT 24 Aug 06 04:32:42 PM PDT 24 41967133 ps
T915 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3837042821 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:43 PM PDT 24 54733279 ps
T916 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207107837 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:44 PM PDT 24 84889593 ps
T917 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361841410 Aug 06 04:33:02 PM PDT 24 Aug 06 04:33:03 PM PDT 24 56235461 ps
T918 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4178484385 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 70347446 ps
T919 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.912488613 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:42 PM PDT 24 64883374 ps
T920 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.679228710 Aug 06 04:33:10 PM PDT 24 Aug 06 04:33:11 PM PDT 24 73274183 ps
T921 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3998445207 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 184481901 ps
T922 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2733642728 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 126910850 ps
T923 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2369214811 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:45 PM PDT 24 161136905 ps
T924 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4291347172 Aug 06 04:33:03 PM PDT 24 Aug 06 04:33:04 PM PDT 24 110842099 ps
T925 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1711074533 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:43 PM PDT 24 377259910 ps
T926 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3534117274 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 133712211 ps
T927 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4143169230 Aug 06 04:33:09 PM PDT 24 Aug 06 04:33:10 PM PDT 24 71831405 ps
T928 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2838351463 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 155990762 ps
T929 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1239620481 Aug 06 04:32:39 PM PDT 24 Aug 06 04:32:40 PM PDT 24 53983214 ps
T930 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1865605918 Aug 06 04:33:03 PM PDT 24 Aug 06 04:33:04 PM PDT 24 105919657 ps
T931 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3801928398 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 402806507 ps
T932 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3636388559 Aug 06 04:32:46 PM PDT 24 Aug 06 04:32:47 PM PDT 24 407423329 ps
T933 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1806703180 Aug 06 04:32:42 PM PDT 24 Aug 06 04:32:44 PM PDT 24 166388754 ps
T934 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4076829518 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 45781831 ps
T935 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2662064248 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:42 PM PDT 24 238911819 ps
T936 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1038133203 Aug 06 04:32:43 PM PDT 24 Aug 06 04:32:44 PM PDT 24 61101166 ps
T937 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4148711005 Aug 06 04:32:44 PM PDT 24 Aug 06 04:32:45 PM PDT 24 28494304 ps
T938 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371459424 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 750708732 ps
T939 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3876200783 Aug 06 04:33:07 PM PDT 24 Aug 06 04:33:09 PM PDT 24 109170002 ps
T940 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2837919494 Aug 06 04:32:36 PM PDT 24 Aug 06 04:32:38 PM PDT 24 337742550 ps
T941 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488726107 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:07 PM PDT 24 30572676 ps
T942 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2591524794 Aug 06 04:33:04 PM PDT 24 Aug 06 04:33:06 PM PDT 24 166565095 ps
T943 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1907048386 Aug 06 04:33:06 PM PDT 24 Aug 06 04:33:07 PM PDT 24 123982186 ps
T944 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233472668 Aug 06 04:33:05 PM PDT 24 Aug 06 04:33:06 PM PDT 24 322046154 ps
T945 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3085279659 Aug 06 04:32:40 PM PDT 24 Aug 06 04:32:41 PM PDT 24 182252102 ps
T946 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.52874869 Aug 06 04:32:46 PM PDT 24 Aug 06 04:32:47 PM PDT 24 27961123 ps
T947 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3573111019 Aug 06 04:33:06 PM PDT 24 Aug 06 04:33:07 PM PDT 24 76032525 ps

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4261268975
Short name T1
Test name
Test status
Simulation time 458445019 ps
CPU time 6.1 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 198384 kb
Host smart-af69d0db-d310-4665-ac86-193c58513fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261268975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4261268975
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.806841330
Short name T23
Test name
Test status
Simulation time 892414657 ps
CPU time 2.52 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:08 PM PDT 24
Peak memory 198336 kb
Host smart-31240fdb-6750-48ad-8974-9a8f99041c17
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806841330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.806841330
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.929240700
Short name T26
Test name
Test status
Simulation time 125206270395 ps
CPU time 861.18 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:48:04 PM PDT 24
Peak memory 198640 kb
Host smart-5930178e-bb90-4bf3-bc4c-8c7fe6161e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=929240700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.929240700
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4004056413
Short name T27
Test name
Test status
Simulation time 141578476 ps
CPU time 1.37 seconds
Started Aug 06 04:31:36 PM PDT 24
Finished Aug 06 04:31:37 PM PDT 24
Peak memory 198564 kb
Host smart-ea0eab35-4866-4dfe-86b2-82cbc6e7979b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004056413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4004056413
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3385865483
Short name T222
Test name
Test status
Simulation time 50784161 ps
CPU time 0.6 seconds
Started Aug 06 04:33:02 PM PDT 24
Finished Aug 06 04:33:02 PM PDT 24
Peak memory 194256 kb
Host smart-0f53711d-4762-4abc-abe8-dbee166f4843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385865483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3385865483
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.921057557
Short name T30
Test name
Test status
Simulation time 202923655 ps
CPU time 0.99 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 215288 kb
Host smart-2dcb71ad-03f3-496d-8574-0b86656fae88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921057557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.921057557
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/31.gpio_full_random.3369495173
Short name T16
Test name
Test status
Simulation time 140546235 ps
CPU time 0.77 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 195164 kb
Host smart-342e1ce7-6849-472d-860c-1c56e42f870d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369495173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3369495173
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3179128839
Short name T91
Test name
Test status
Simulation time 67551568 ps
CPU time 1.32 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 198536 kb
Host smart-a298f6ed-443e-4df8-9960-ce7617932e68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179128839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3179128839
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2718873090
Short name T95
Test name
Test status
Simulation time 26676838 ps
CPU time 0.67 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 195640 kb
Host smart-b13e4dbc-bddb-4d34-a7b1-7e628775e40a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718873090 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2718873090
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.160597600
Short name T810
Test name
Test status
Simulation time 412040355 ps
CPU time 1.33 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 198652 kb
Host smart-bc5444f8-e1dd-4d96-9f72-e40e64d41c2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160597600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.160597600
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1665602159
Short name T818
Test name
Test status
Simulation time 114866272 ps
CPU time 0.83 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 196744 kb
Host smart-c980bcd7-9a3e-417e-97aa-011e74dd4185
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665602159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1665602159
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1442009132
Short name T844
Test name
Test status
Simulation time 196903040 ps
CPU time 0.65 seconds
Started Aug 06 04:31:40 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 195872 kb
Host smart-8df4675f-c8a5-4986-b915-e6318d295436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442009132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1442009132
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2747807254
Short name T738
Test name
Test status
Simulation time 66461595 ps
CPU time 0.87 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 198440 kb
Host smart-1a448266-d7ce-4242-ba9d-f9efbb08e4ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747807254 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2747807254
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.462859204
Short name T784
Test name
Test status
Simulation time 11499904 ps
CPU time 0.57 seconds
Started Aug 06 04:31:36 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 194532 kb
Host smart-1f2767ca-19d6-47ca-bfd9-8eec1bd2fbed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462859204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.462859204
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.183766298
Short name T786
Test name
Test status
Simulation time 68723947 ps
CPU time 0.56 seconds
Started Aug 06 04:31:39 PM PDT 24
Finished Aug 06 04:31:40 PM PDT 24
Peak memory 194944 kb
Host smart-fc5e96b7-fc46-4b51-bbe5-c860b1c94d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183766298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.183766298
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2150896612
Short name T796
Test name
Test status
Simulation time 746463181 ps
CPU time 2.27 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 198560 kb
Host smart-46e710bb-0fd3-4700-bb63-96b00ad105ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150896612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2150896612
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3724251601
Short name T92
Test name
Test status
Simulation time 19401433 ps
CPU time 0.84 seconds
Started Aug 06 04:31:40 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 196568 kb
Host smart-30a1e7f2-1ac6-4163-b36b-d558a201143e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724251601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3724251601
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3253926677
Short name T772
Test name
Test status
Simulation time 58547513 ps
CPU time 2.06 seconds
Started Aug 06 04:31:32 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 197092 kb
Host smart-2c9e7b85-78d8-4722-9350-d439daf73c5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253926677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3253926677
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3531737510
Short name T776
Test name
Test status
Simulation time 35680754 ps
CPU time 0.6 seconds
Started Aug 06 04:31:36 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 194912 kb
Host smart-25d05a75-2fab-4c15-b03c-686c18643edd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531737510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3531737510
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2226308154
Short name T734
Test name
Test status
Simulation time 85137986 ps
CPU time 0.8 seconds
Started Aug 06 04:31:37 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 198452 kb
Host smart-5ccaf5c9-513c-445c-935a-ee0132a88036
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226308154 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2226308154
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3913289851
Short name T753
Test name
Test status
Simulation time 31162872 ps
CPU time 0.54 seconds
Started Aug 06 04:31:30 PM PDT 24
Finished Aug 06 04:31:31 PM PDT 24
Peak memory 195120 kb
Host smart-20e2ac4e-6a89-4f1b-9617-c1b651fcba36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913289851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3913289851
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4294745848
Short name T736
Test name
Test status
Simulation time 31218477 ps
CPU time 0.6 seconds
Started Aug 06 04:31:40 PM PDT 24
Finished Aug 06 04:31:40 PM PDT 24
Peak memory 194352 kb
Host smart-9363a343-45aa-476a-9958-347a2a9a1104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294745848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4294745848
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2588404278
Short name T94
Test name
Test status
Simulation time 17316312 ps
CPU time 0.75 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 197632 kb
Host smart-5721452e-025b-4018-a55c-8b019981d981
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588404278 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2588404278
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2158853659
Short name T732
Test name
Test status
Simulation time 436715728 ps
CPU time 2.02 seconds
Started Aug 06 04:31:36 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 198604 kb
Host smart-0b2ea9a4-7b52-49a3-8cf8-50918a395394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158853659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2158853659
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3133116038
Short name T29
Test name
Test status
Simulation time 266458258 ps
CPU time 1.33 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:36 PM PDT 24
Peak memory 198652 kb
Host smart-b8644031-7375-48db-b161-b1b566e58020
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133116038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3133116038
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3511661950
Short name T840
Test name
Test status
Simulation time 78458046 ps
CPU time 0.94 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 198456 kb
Host smart-3bd303dc-d8ad-4bc0-87ec-93acce1e3d7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511661950 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3511661950
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4180323791
Short name T87
Test name
Test status
Simulation time 92111049 ps
CPU time 0.6 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 194952 kb
Host smart-91ef3cbe-ed35-4a77-ae2c-178da5721d25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180323791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.4180323791
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2220937396
Short name T820
Test name
Test status
Simulation time 27099500 ps
CPU time 0.57 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 194216 kb
Host smart-831d0bce-9ac1-45e4-a8c1-762a8b4d0ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220937396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2220937396
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2288957578
Short name T803
Test name
Test status
Simulation time 91787763 ps
CPU time 0.76 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 196512 kb
Host smart-bc659751-e092-411f-8e8a-e9f508be7a50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288957578 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2288957578
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.563866903
Short name T741
Test name
Test status
Simulation time 155690056 ps
CPU time 2.05 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198712 kb
Host smart-2811a3f1-e157-447c-b2f5-bbd26cd84d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563866903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.563866903
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4107625708
Short name T773
Test name
Test status
Simulation time 802086724 ps
CPU time 1.07 seconds
Started Aug 06 04:32:03 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 198572 kb
Host smart-0eea4d1e-4acb-4076-873a-e95a268b4848
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107625708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4107625708
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3334390561
Short name T762
Test name
Test status
Simulation time 25857405 ps
CPU time 0.82 seconds
Started Aug 06 04:32:04 PM PDT 24
Finished Aug 06 04:32:05 PM PDT 24
Peak memory 198432 kb
Host smart-5e2c90a3-a347-4c1f-83c4-c7bdc6340595
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334390561 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3334390561
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3602530847
Short name T798
Test name
Test status
Simulation time 35110999 ps
CPU time 0.57 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 194912 kb
Host smart-905e9bb0-e129-4a22-883d-9b8c5c773f53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602530847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3602530847
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.512763883
Short name T764
Test name
Test status
Simulation time 24636092 ps
CPU time 0.56 seconds
Started Aug 06 04:32:12 PM PDT 24
Finished Aug 06 04:32:12 PM PDT 24
Peak memory 194276 kb
Host smart-11f99da8-f7d4-4f0a-a232-f54fea972c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512763883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.512763883
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4231310255
Short name T83
Test name
Test status
Simulation time 31319506 ps
CPU time 0.74 seconds
Started Aug 06 04:32:02 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 197472 kb
Host smart-20f10958-ec76-4002-b8f5-8fc059cc6028
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231310255 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4231310255
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1837868059
Short name T758
Test name
Test status
Simulation time 242609783 ps
CPU time 2.64 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198616 kb
Host smart-52bfc783-8ce3-4ccf-be28-86fa5afe22fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837868059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1837868059
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1124364184
Short name T811
Test name
Test status
Simulation time 113276531 ps
CPU time 1.45 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198428 kb
Host smart-f0fbf48d-bde9-4613-82ac-9e37cc411952
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124364184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1124364184
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2355316163
Short name T831
Test name
Test status
Simulation time 62545776 ps
CPU time 1.54 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198540 kb
Host smart-d12d5752-340d-42a9-9062-912d70c4f7d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355316163 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2355316163
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.348704586
Short name T737
Test name
Test status
Simulation time 21637242 ps
CPU time 0.59 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 195120 kb
Host smart-1915fa9a-1ba2-435a-8e0f-68b38410099b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348704586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.348704586
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2112414832
Short name T747
Test name
Test status
Simulation time 39863400 ps
CPU time 0.57 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194360 kb
Host smart-3eca03bc-192a-4a09-9a95-1baf0d95d783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112414832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2112414832
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3422344008
Short name T97
Test name
Test status
Simulation time 373271802 ps
CPU time 0.73 seconds
Started Aug 06 04:32:05 PM PDT 24
Finished Aug 06 04:32:06 PM PDT 24
Peak memory 196748 kb
Host smart-f8267a38-fe43-4c8d-be6a-0f0144747f26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422344008 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3422344008
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.446623098
Short name T774
Test name
Test status
Simulation time 619262870 ps
CPU time 1.36 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 198672 kb
Host smart-5b8d28df-27ac-4ebe-ad5b-0afdd618bb3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446623098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.446623098
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.170453271
Short name T781
Test name
Test status
Simulation time 52037613 ps
CPU time 0.87 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 197804 kb
Host smart-c4d2cf5d-83d6-4da9-89c5-ddea4b9672b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170453271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.170453271
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3110766345
Short name T834
Test name
Test status
Simulation time 26082393 ps
CPU time 0.73 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 198476 kb
Host smart-df214ba9-ee7e-4b6e-a313-152e4733b90b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110766345 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3110766345
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4059553519
Short name T805
Test name
Test status
Simulation time 29867255 ps
CPU time 0.55 seconds
Started Aug 06 04:32:32 PM PDT 24
Finished Aug 06 04:32:33 PM PDT 24
Peak memory 193864 kb
Host smart-4c13bc3d-e4fb-4405-a3c5-f944fc942828
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059553519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4059553519
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.113675809
Short name T817
Test name
Test status
Simulation time 17190067 ps
CPU time 0.62 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194416 kb
Host smart-fae59c15-68ad-4eb3-a406-3bc714adc37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113675809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.113675809
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3218031893
Short name T814
Test name
Test status
Simulation time 29200923 ps
CPU time 0.6 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:33 PM PDT 24
Peak memory 194956 kb
Host smart-e734f2f6-225e-4f1d-968c-6cfb9c3e8ca7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218031893 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3218031893
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1964397508
Short name T720
Test name
Test status
Simulation time 70283024 ps
CPU time 1.04 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 198484 kb
Host smart-d38010d1-d755-4017-b25a-0a61b2c08473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964397508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1964397508
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2463447183
Short name T808
Test name
Test status
Simulation time 136339953 ps
CPU time 1.11 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 198640 kb
Host smart-a2a0f352-be64-4810-945d-b85000d9956e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463447183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2463447183
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2658749709
Short name T790
Test name
Test status
Simulation time 84438785 ps
CPU time 0.64 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 197036 kb
Host smart-e9a91874-00db-4a90-afbc-e6b816919dd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658749709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2658749709
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.533300860
Short name T821
Test name
Test status
Simulation time 14826500 ps
CPU time 0.57 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 195136 kb
Host smart-42adbf79-85dc-4881-832c-3e06eabebd81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533300860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.533300860
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.909548993
Short name T759
Test name
Test status
Simulation time 16376180 ps
CPU time 0.6 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194452 kb
Host smart-f65ac4b5-af72-4320-8bc1-44c5964bc345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909548993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.909548993
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1958645091
Short name T99
Test name
Test status
Simulation time 126036312 ps
CPU time 0.78 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 196852 kb
Host smart-4d118999-f962-4f48-88da-27cb1899f2a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958645091 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1958645091
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.963143451
Short name T749
Test name
Test status
Simulation time 44176332 ps
CPU time 2.18 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 198568 kb
Host smart-fd4e84c0-ece9-412b-9fab-ac8946e6ed21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963143451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.963143451
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2327785576
Short name T761
Test name
Test status
Simulation time 107035948 ps
CPU time 0.92 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 197464 kb
Host smart-89081158-51a5-4938-b46d-7e2cb7d8bde8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327785576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2327785576
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1882734657
Short name T755
Test name
Test status
Simulation time 103877077 ps
CPU time 1.2 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:38 PM PDT 24
Peak memory 198592 kb
Host smart-b51d08dc-04d9-4972-99d1-9e99850a9731
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882734657 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1882734657
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2303996924
Short name T112
Test name
Test status
Simulation time 14797387 ps
CPU time 0.66 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 196044 kb
Host smart-63472cf0-aa7c-46e3-8f32-d98a6e02b9c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303996924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2303996924
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1586776221
Short name T727
Test name
Test status
Simulation time 15587940 ps
CPU time 0.59 seconds
Started Aug 06 04:32:37 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 194384 kb
Host smart-6c876b98-40f2-40d3-92e9-5b662d0b99c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586776221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1586776221
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1317186892
Short name T801
Test name
Test status
Simulation time 15600130 ps
CPU time 0.69 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 195520 kb
Host smart-cc410519-ff4b-4be5-be1e-286432a52d86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317186892 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1317186892
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1581006445
Short name T729
Test name
Test status
Simulation time 32179363 ps
CPU time 1.62 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 198728 kb
Host smart-426f9951-267b-42f1-ae00-346c87497f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581006445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1581006445
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1372735943
Short name T791
Test name
Test status
Simulation time 48843646 ps
CPU time 0.89 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 198180 kb
Host smart-30201cba-b503-4365-a9b1-46397ce1778d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372735943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1372735943
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.996594511
Short name T800
Test name
Test status
Simulation time 129404602 ps
CPU time 1.03 seconds
Started Aug 06 04:32:37 PM PDT 24
Finished Aug 06 04:32:38 PM PDT 24
Peak memory 198484 kb
Host smart-96e69211-b49a-45b4-8b87-65f2cd1ce010
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996594511 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.996594511
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.663715058
Short name T793
Test name
Test status
Simulation time 44112830 ps
CPU time 0.55 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 193816 kb
Host smart-0733671d-f904-4cb1-a4e2-de0db092c45b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663715058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.663715058
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1101688224
Short name T760
Test name
Test status
Simulation time 47494127 ps
CPU time 0.55 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 194208 kb
Host smart-8396bf24-0d22-46c6-9fb6-28b9a8dd0c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101688224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1101688224
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4040463550
Short name T96
Test name
Test status
Simulation time 74535207 ps
CPU time 0.65 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 196180 kb
Host smart-72c98a6d-e73b-4c7b-9b96-5ac038d061de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040463550 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4040463550
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1778965892
Short name T827
Test name
Test status
Simulation time 53158208 ps
CPU time 1.22 seconds
Started Aug 06 04:32:38 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 198620 kb
Host smart-01da013e-e927-4a40-9982-348da5946162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778965892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1778965892
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.748661770
Short name T799
Test name
Test status
Simulation time 174137021 ps
CPU time 1.14 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 198968 kb
Host smart-b5fbf872-0a3d-46c5-affd-c2373a873b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748661770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.748661770
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.560246805
Short name T835
Test name
Test status
Simulation time 23197111 ps
CPU time 0.74 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 198520 kb
Host smart-54654994-167d-43b4-a791-0690500c1132
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560246805 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.560246805
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1617621471
Short name T89
Test name
Test status
Simulation time 14595022 ps
CPU time 0.57 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 196020 kb
Host smart-4dfc6805-7dea-47e5-a121-767abbfef173
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617621471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1617621471
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.462842566
Short name T719
Test name
Test status
Simulation time 24350669 ps
CPU time 0.59 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194276 kb
Host smart-42a7c904-3b81-45f3-8b8c-3159d02dce5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462842566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.462842566
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4096299991
Short name T100
Test name
Test status
Simulation time 63476526 ps
CPU time 0.87 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 197900 kb
Host smart-b60812f7-1e35-41e2-a24f-40e9e9b51351
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096299991 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4096299991
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3089687417
Short name T787
Test name
Test status
Simulation time 189688242 ps
CPU time 2.09 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 198660 kb
Host smart-2bddbba3-d1b9-4ebc-a520-997281a8d91d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089687417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3089687417
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4252805085
Short name T113
Test name
Test status
Simulation time 99439809 ps
CPU time 1.36 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 198568 kb
Host smart-956943b6-9dff-44f6-b5a8-e34b650870d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252805085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.4252805085
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.242820212
Short name T778
Test name
Test status
Simulation time 99231662 ps
CPU time 0.84 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 198500 kb
Host smart-718f63a9-d6a3-41fd-a140-793c1aa0aa39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242820212 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.242820212
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2870539229
Short name T111
Test name
Test status
Simulation time 13315477 ps
CPU time 0.61 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 195380 kb
Host smart-9ef023c6-ea49-4cec-82f0-bd696b11e0ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870539229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2870539229
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3365354188
Short name T825
Test name
Test status
Simulation time 48295441 ps
CPU time 0.55 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194228 kb
Host smart-608ac43d-3e30-4aad-8a31-2d57ddab34b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365354188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3365354188
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2287545743
Short name T847
Test name
Test status
Simulation time 33695344 ps
CPU time 0.81 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 196988 kb
Host smart-a27bd269-9b36-4a71-b140-0c90bff10b2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287545743 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2287545743
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3589597176
Short name T744
Test name
Test status
Simulation time 109377798 ps
CPU time 1.53 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 198680 kb
Host smart-b4af59f7-9520-4327-9d61-410209fd93fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589597176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3589597176
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1410334192
Short name T823
Test name
Test status
Simulation time 209573536 ps
CPU time 1.35 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 198552 kb
Host smart-b775ec55-ac97-4a18-a388-f0ba23450cde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410334192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1410334192
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1770935473
Short name T841
Test name
Test status
Simulation time 44068623 ps
CPU time 1.04 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 198388 kb
Host smart-8157adc1-f790-4674-a086-554d4c6f76de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770935473 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1770935473
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2300464459
Short name T86
Test name
Test status
Simulation time 14091088 ps
CPU time 0.6 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 195348 kb
Host smart-b719402f-24c7-42d8-b1ab-527e2c40cf5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300464459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2300464459
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.144555365
Short name T771
Test name
Test status
Simulation time 42735509 ps
CPU time 0.58 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194996 kb
Host smart-b9bd1100-eb96-4989-9443-494a459cf5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144555365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.144555365
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2516607482
Short name T806
Test name
Test status
Simulation time 82184353 ps
CPU time 0.65 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 195108 kb
Host smart-c9ce565e-ed07-478c-aa69-8bf48e99e370
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516607482 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2516607482
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1668186101
Short name T725
Test name
Test status
Simulation time 137236159 ps
CPU time 2.82 seconds
Started Aug 06 04:32:32 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 198564 kb
Host smart-011150f7-d44b-4540-b0c7-7ec3dd5e90e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668186101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1668186101
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1305224354
Short name T843
Test name
Test status
Simulation time 72513911 ps
CPU time 1.17 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 198292 kb
Host smart-b0a0ecbf-13c5-4573-80ea-d94fe2ead715
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305224354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1305224354
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3401963622
Short name T757
Test name
Test status
Simulation time 33121171 ps
CPU time 0.83 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 196696 kb
Host smart-3a2e8a1f-df58-4c47-9ec2-bb8c4a09a8ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401963622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3401963622
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4140956933
Short name T785
Test name
Test status
Simulation time 519356454 ps
CPU time 3.24 seconds
Started Aug 06 04:31:37 PM PDT 24
Finished Aug 06 04:31:41 PM PDT 24
Peak memory 198520 kb
Host smart-ed0e03e1-3145-414a-93b8-0b9038d60cac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140956933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4140956933
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2840826603
Short name T110
Test name
Test status
Simulation time 22234348 ps
CPU time 0.66 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:33 PM PDT 24
Peak memory 196068 kb
Host smart-07fb6220-bd3b-4ecc-bb6d-bf52c99afe94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840826603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2840826603
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2966301327
Short name T789
Test name
Test status
Simulation time 112540961 ps
CPU time 0.95 seconds
Started Aug 06 04:31:37 PM PDT 24
Finished Aug 06 04:31:38 PM PDT 24
Peak memory 198460 kb
Host smart-8989ee8b-6bc3-44f6-8e28-4e6a5e263da4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966301327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2966301327
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1199720964
Short name T85
Test name
Test status
Simulation time 17013334 ps
CPU time 0.59 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 196008 kb
Host smart-1ea5ea65-0e61-461d-85ca-67791dcca3ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199720964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1199720964
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3675915593
Short name T735
Test name
Test status
Simulation time 40496087 ps
CPU time 0.55 seconds
Started Aug 06 04:31:33 PM PDT 24
Finished Aug 06 04:31:34 PM PDT 24
Peak memory 194292 kb
Host smart-2da006a5-5dbf-4d63-b8ed-12fea528efef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675915593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3675915593
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4042756955
Short name T830
Test name
Test status
Simulation time 35199229 ps
CPU time 0.82 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 196912 kb
Host smart-cf0c00ad-ff05-4865-87e9-07b169ef2f4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042756955 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4042756955
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1429699361
Short name T792
Test name
Test status
Simulation time 54357638 ps
CPU time 1.39 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 198412 kb
Host smart-4744f5fb-300e-4517-a78e-a91590a22258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429699361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1429699361
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2812117483
Short name T815
Test name
Test status
Simulation time 17805429 ps
CPU time 0.55 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194324 kb
Host smart-8c051b93-27b9-40dc-9458-dd86c341a986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812117483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2812117483
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.58334613
Short name T724
Test name
Test status
Simulation time 34729891 ps
CPU time 0.6 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194308 kb
Host smart-e1c83f15-1ed8-41b9-99db-2cda76afdde9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58334613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.58334613
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3241331843
Short name T783
Test name
Test status
Simulation time 29752423 ps
CPU time 0.6 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 194420 kb
Host smart-0801247b-205d-4506-b132-7b267ca6d14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241331843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3241331843
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2524247115
Short name T768
Test name
Test status
Simulation time 15157965 ps
CPU time 0.55 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194976 kb
Host smart-f6fba62f-2134-4419-8cb9-a74e3440ad13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524247115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2524247115
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2609873974
Short name T837
Test name
Test status
Simulation time 11739500 ps
CPU time 0.57 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194372 kb
Host smart-a12e8e46-a785-45bd-9ec8-847b2ecf7391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609873974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2609873974
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2849040359
Short name T765
Test name
Test status
Simulation time 12035120 ps
CPU time 0.57 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194336 kb
Host smart-fbb00d08-d186-4867-a5c4-d2cd3f83344e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849040359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2849040359
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1798276119
Short name T795
Test name
Test status
Simulation time 19083165 ps
CPU time 0.6 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194248 kb
Host smart-f19cd5da-8fed-4eaf-ad39-85826a7e9ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798276119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1798276119
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3649894794
Short name T730
Test name
Test status
Simulation time 13128495 ps
CPU time 0.55 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194328 kb
Host smart-065391b0-a74c-4ed0-a14a-da8979ce76c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649894794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3649894794
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4012488579
Short name T779
Test name
Test status
Simulation time 16120902 ps
CPU time 0.6 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194944 kb
Host smart-04c9e21d-3ba2-4425-af17-e75de81b5cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012488579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4012488579
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3193401542
Short name T826
Test name
Test status
Simulation time 38825032 ps
CPU time 0.58 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194992 kb
Host smart-7ee6dab9-6077-44fc-9644-dc0039bca6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193401542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3193401542
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1222568075
Short name T79
Test name
Test status
Simulation time 60133727 ps
CPU time 0.64 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 195244 kb
Host smart-4420b533-4100-4940-bd27-83031faa76e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222568075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1222568075
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1060844058
Short name T802
Test name
Test status
Simulation time 368875343 ps
CPU time 2.24 seconds
Started Aug 06 04:32:05 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 198580 kb
Host smart-7b7ed644-cd98-428b-a171-1973513d1350
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060844058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1060844058
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.138199965
Short name T82
Test name
Test status
Simulation time 22300041 ps
CPU time 0.72 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 195548 kb
Host smart-872bc3d4-ad39-48bf-9d08-bfa83f4fba2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138199965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.138199965
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1348746195
Short name T726
Test name
Test status
Simulation time 52807195 ps
CPU time 1.32 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 199024 kb
Host smart-316dd9e6-97fc-4dc4-abc1-ea8b8de9230b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348746195 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1348746195
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2243767826
Short name T90
Test name
Test status
Simulation time 37235512 ps
CPU time 0.56 seconds
Started Aug 06 04:31:34 PM PDT 24
Finished Aug 06 04:31:35 PM PDT 24
Peak memory 193904 kb
Host smart-f2f603cd-36cd-4956-9b07-b74b744f73ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243767826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2243767826
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2644750207
Short name T836
Test name
Test status
Simulation time 12184468 ps
CPU time 0.61 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 195052 kb
Host smart-54227b25-b219-40ab-bc85-992d59016e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644750207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2644750207
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.935037291
Short name T813
Test name
Test status
Simulation time 47602969 ps
CPU time 0.65 seconds
Started Aug 06 04:32:03 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 195572 kb
Host smart-48e73d72-18ef-4606-b810-232274610c5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935037291 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.935037291
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1276289625
Short name T752
Test name
Test status
Simulation time 73763745 ps
CPU time 1.05 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 198584 kb
Host smart-bf919a3b-3c13-44c7-ab56-ab5b49c4d190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276289625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1276289625
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2433152745
Short name T37
Test name
Test status
Simulation time 541400262 ps
CPU time 1.15 seconds
Started Aug 06 04:32:04 PM PDT 24
Finished Aug 06 04:32:05 PM PDT 24
Peak memory 198656 kb
Host smart-9ad5a452-a78a-4e42-b711-e31c8ad5a001
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433152745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2433152745
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1251638322
Short name T777
Test name
Test status
Simulation time 18261089 ps
CPU time 0.58 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194364 kb
Host smart-3f907238-ba8e-4281-83ea-3fc70c16b99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251638322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1251638322
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3725917816
Short name T723
Test name
Test status
Simulation time 30617534 ps
CPU time 0.63 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194276 kb
Host smart-eb0c543a-88c6-453f-a038-4bccab6820d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725917816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3725917816
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1323306950
Short name T750
Test name
Test status
Simulation time 53691756 ps
CPU time 0.58 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194356 kb
Host smart-7ce5c63e-44fd-42b6-a85a-333784f518cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323306950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1323306950
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2794557193
Short name T769
Test name
Test status
Simulation time 50158582 ps
CPU time 0.57 seconds
Started Aug 06 04:32:33 PM PDT 24
Finished Aug 06 04:32:34 PM PDT 24
Peak memory 194368 kb
Host smart-d321af66-3516-40de-a58c-418b49e0febc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794557193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2794557193
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1982788374
Short name T745
Test name
Test status
Simulation time 14251146 ps
CPU time 0.57 seconds
Started Aug 06 04:32:34 PM PDT 24
Finished Aug 06 04:32:35 PM PDT 24
Peak memory 194344 kb
Host smart-9da67c63-9a42-4486-a45a-2f565598883c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982788374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1982788374
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2021259560
Short name T721
Test name
Test status
Simulation time 15866774 ps
CPU time 0.62 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 194188 kb
Host smart-abf2d697-21eb-4551-ac55-7427d3f612e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021259560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2021259560
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3977890624
Short name T740
Test name
Test status
Simulation time 36787985 ps
CPU time 0.56 seconds
Started Aug 06 04:32:38 PM PDT 24
Finished Aug 06 04:32:39 PM PDT 24
Peak memory 194948 kb
Host smart-8696155d-2c7b-4b22-a469-ea13bf385a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977890624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3977890624
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1392028205
Short name T742
Test name
Test status
Simulation time 23768532 ps
CPU time 0.6 seconds
Started Aug 06 04:32:38 PM PDT 24
Finished Aug 06 04:32:39 PM PDT 24
Peak memory 194964 kb
Host smart-6261b078-4dd0-41f0-ab45-9a6fca9712b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392028205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1392028205
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3695927812
Short name T829
Test name
Test status
Simulation time 34591291 ps
CPU time 0.57 seconds
Started Aug 06 04:32:38 PM PDT 24
Finished Aug 06 04:32:39 PM PDT 24
Peak memory 194968 kb
Host smart-1430cf8c-0953-49df-bbd2-88dd0d958b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695927812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3695927812
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2409366456
Short name T767
Test name
Test status
Simulation time 13219370 ps
CPU time 0.59 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 194344 kb
Host smart-d9607d66-cd2f-47ac-ae29-89ffc5ec9d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409366456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2409366456
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3526100674
Short name T78
Test name
Test status
Simulation time 54846017 ps
CPU time 0.79 seconds
Started Aug 06 04:32:03 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 196664 kb
Host smart-3969518d-39e3-464a-8ff7-031abb09277d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526100674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3526100674
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2243236326
Short name T754
Test name
Test status
Simulation time 35736339 ps
CPU time 1.35 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 197256 kb
Host smart-6195a5a1-1d79-4843-a8b5-cb62eafd29ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243236326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2243236326
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4076066028
Short name T770
Test name
Test status
Simulation time 14434459 ps
CPU time 0.59 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 194928 kb
Host smart-9430eb46-e68b-496f-87aa-ce88fe882325
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076066028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4076066028
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1575736402
Short name T807
Test name
Test status
Simulation time 173533798 ps
CPU time 1.29 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198624 kb
Host smart-bf2a2972-cf0c-44e4-81b5-61dc56f9a81c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575736402 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1575736402
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3296033635
Short name T766
Test name
Test status
Simulation time 13907453 ps
CPU time 0.54 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 193840 kb
Host smart-fd92817d-3637-4b75-b485-54db527b35d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296033635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3296033635
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2044924899
Short name T812
Test name
Test status
Simulation time 14598377 ps
CPU time 0.58 seconds
Started Aug 06 04:32:10 PM PDT 24
Finished Aug 06 04:32:11 PM PDT 24
Peak memory 194916 kb
Host smart-6cd3199e-eb01-4d91-a7c9-592c935bfa37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044924899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2044924899
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3588398373
Short name T80
Test name
Test status
Simulation time 19142596 ps
CPU time 0.77 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 196804 kb
Host smart-3826a8a3-89f4-4f6b-bf5b-aa8089e947e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588398373 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3588398373
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3339136078
Short name T743
Test name
Test status
Simulation time 376687154 ps
CPU time 2.03 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198568 kb
Host smart-fa90c563-63b8-4dac-bc5a-d3f286669449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339136078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3339136078
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3738573938
Short name T40
Test name
Test status
Simulation time 243603382 ps
CPU time 1.28 seconds
Started Aug 06 04:32:05 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 198660 kb
Host smart-8296a164-3598-410c-b5c4-35b6dcb0cd77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738573938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3738573938
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2513013066
Short name T751
Test name
Test status
Simulation time 16520761 ps
CPU time 0.6 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 194168 kb
Host smart-a041b4ed-9d0b-4cc5-92c7-b12754dc3663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513013066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2513013066
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2374701092
Short name T718
Test name
Test status
Simulation time 17478013 ps
CPU time 0.59 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 194376 kb
Host smart-a0a5258a-3d00-4b46-8778-ece8d7570f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374701092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2374701092
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2541990776
Short name T804
Test name
Test status
Simulation time 20709485 ps
CPU time 0.59 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 194372 kb
Host smart-d4fae4cb-bade-499e-a06f-6dcbc9900fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541990776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2541990776
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3993841921
Short name T780
Test name
Test status
Simulation time 12996528 ps
CPU time 0.55 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 194236 kb
Host smart-beca361c-f20f-4f3d-a260-c3aee6cbad99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993841921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3993841921
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.438757041
Short name T824
Test name
Test status
Simulation time 85011003 ps
CPU time 0.56 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194904 kb
Host smart-762b62a9-2deb-4886-96f2-9ac774a4cfe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438757041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.438757041
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.757005914
Short name T833
Test name
Test status
Simulation time 12676550 ps
CPU time 0.58 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 194428 kb
Host smart-0b968efb-07da-4260-9d11-378fa0eeb4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757005914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.757005914
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2030187848
Short name T739
Test name
Test status
Simulation time 14547535 ps
CPU time 0.64 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 195016 kb
Host smart-31e3939c-4696-4bc2-b2e2-c0adf473e84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030187848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2030187848
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3323684287
Short name T832
Test name
Test status
Simulation time 55083092 ps
CPU time 0.69 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 195076 kb
Host smart-8ff3426b-2a28-4e9d-aa08-03bf13e08f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323684287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3323684287
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1499525831
Short name T782
Test name
Test status
Simulation time 14469505 ps
CPU time 0.6 seconds
Started Aug 06 04:32:41 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 194280 kb
Host smart-966ab0c9-deb4-41a6-a03d-57d3ef184c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499525831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1499525831
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2445300575
Short name T733
Test name
Test status
Simulation time 25541525 ps
CPU time 0.6 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 194300 kb
Host smart-974adfe9-8072-41f4-be58-06479991cefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445300575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2445300575
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1700219950
Short name T731
Test name
Test status
Simulation time 196429151 ps
CPU time 1.77 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198672 kb
Host smart-8001cb0b-7bfa-4f39-bbe9-6eb942b459ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700219950 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1700219950
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1716438541
Short name T839
Test name
Test status
Simulation time 23295293 ps
CPU time 0.57 seconds
Started Aug 06 04:32:04 PM PDT 24
Finished Aug 06 04:32:05 PM PDT 24
Peak memory 193880 kb
Host smart-47e296b4-8b9e-48e4-af92-1058c1df7791
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716438541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1716438541
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.725393168
Short name T748
Test name
Test status
Simulation time 72331319 ps
CPU time 0.6 seconds
Started Aug 06 04:32:02 PM PDT 24
Finished Aug 06 04:32:03 PM PDT 24
Peak memory 194412 kb
Host smart-bd7dd3b5-fe3e-4d09-811f-4a5547b6b122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725393168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.725393168
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3408480600
Short name T98
Test name
Test status
Simulation time 39457436 ps
CPU time 0.66 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 196060 kb
Host smart-e55c336a-e7e3-4de6-a9e2-d5975f66c5af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408480600 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3408480600
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4147480412
Short name T816
Test name
Test status
Simulation time 131319774 ps
CPU time 1.58 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198664 kb
Host smart-cea256ed-b3e1-45b4-bf5f-f60005721c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147480412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4147480412
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.669823638
Short name T36
Test name
Test status
Simulation time 65031902 ps
CPU time 0.88 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198384 kb
Host smart-b6306e7d-f3b9-4731-b4d3-e284d6fcf4f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669823638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.669823638
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3393485244
Short name T775
Test name
Test status
Simulation time 145472337 ps
CPU time 0.88 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 198400 kb
Host smart-3293de28-42d0-4faf-a17c-991f4d3e90fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393485244 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3393485244
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3485073300
Short name T81
Test name
Test status
Simulation time 28861656 ps
CPU time 0.53 seconds
Started Aug 06 04:32:05 PM PDT 24
Finished Aug 06 04:32:05 PM PDT 24
Peak memory 193916 kb
Host smart-7001b431-2895-40b7-9f05-5348974e7c4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485073300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3485073300
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3590504616
Short name T756
Test name
Test status
Simulation time 247302793 ps
CPU time 0.62 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 195004 kb
Host smart-a2a82a8b-5b72-461e-8c4b-ac63df1f770b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590504616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3590504616
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.43299054
Short name T846
Test name
Test status
Simulation time 77727604 ps
CPU time 0.66 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 195372 kb
Host smart-e2acef1e-0bcf-4804-96b5-b7c844b51b90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43299054 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.gpio_same_csr_outstanding.43299054
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.813083270
Short name T722
Test name
Test status
Simulation time 171088611 ps
CPU time 1.25 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198704 kb
Host smart-4a87e5c5-9eb6-4524-9b5c-210fac9f95f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813083270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.813083270
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1002956007
Short name T38
Test name
Test status
Simulation time 46075611 ps
CPU time 0.91 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198128 kb
Host smart-70b84fe8-790e-44d4-a160-4168c8a8b0c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002956007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1002956007
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2029127921
Short name T763
Test name
Test status
Simulation time 44194395 ps
CPU time 0.71 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 192100 kb
Host smart-2973b5dd-b047-4199-b69f-cd9697bbebe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029127921 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2029127921
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2119889623
Short name T84
Test name
Test status
Simulation time 94075274 ps
CPU time 0.63 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 195348 kb
Host smart-9be24127-b847-4f84-b6b1-7f1ddd48b0f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119889623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2119889623
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1834615963
Short name T794
Test name
Test status
Simulation time 11976324 ps
CPU time 0.58 seconds
Started Aug 06 04:32:03 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 194520 kb
Host smart-221de645-2096-4ca7-b731-89da9190622d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834615963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1834615963
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1538950693
Short name T819
Test name
Test status
Simulation time 20726347 ps
CPU time 0.84 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198344 kb
Host smart-b5b9c613-3396-4400-9627-506059b4f10b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538950693 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1538950693
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.62598370
Short name T797
Test name
Test status
Simulation time 172265580 ps
CPU time 2.65 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 198656 kb
Host smart-a8f2c949-05ab-4b05-be3d-61e106b8742c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62598370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.62598370
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3756111009
Short name T822
Test name
Test status
Simulation time 75765075 ps
CPU time 1.08 seconds
Started Aug 06 04:32:03 PM PDT 24
Finished Aug 06 04:32:04 PM PDT 24
Peak memory 198620 kb
Host smart-7f80a96f-6a4c-4a0a-af33-add286117b4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756111009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3756111009
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.657292832
Short name T845
Test name
Test status
Simulation time 29513486 ps
CPU time 0.88 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198516 kb
Host smart-8182826c-ada1-4982-851f-707ded941be7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657292832 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.657292832
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3143854568
Short name T88
Test name
Test status
Simulation time 18314078 ps
CPU time 0.58 seconds
Started Aug 06 04:32:04 PM PDT 24
Finished Aug 06 04:32:05 PM PDT 24
Peak memory 194144 kb
Host smart-a9d59d4a-da7d-49a2-afbf-48011cff4dfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143854568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3143854568
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1444581785
Short name T746
Test name
Test status
Simulation time 16220824 ps
CPU time 0.62 seconds
Started Aug 06 04:32:09 PM PDT 24
Finished Aug 06 04:32:10 PM PDT 24
Peak memory 194356 kb
Host smart-8ebe2b0b-171e-478e-95f5-2bc3e334f206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444581785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1444581785
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.476413880
Short name T93
Test name
Test status
Simulation time 377832948 ps
CPU time 0.85 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 197396 kb
Host smart-e7898655-0456-4eba-8ca2-e805ff316795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476413880 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.476413880
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.514867155
Short name T838
Test name
Test status
Simulation time 1164638736 ps
CPU time 1.58 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198472 kb
Host smart-66a8df5b-a3f0-44ad-9b86-74877f8032b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514867155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.514867155
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2703978000
Short name T39
Test name
Test status
Simulation time 49877733 ps
CPU time 0.89 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 197508 kb
Host smart-2c9198a5-eed0-496c-8751-5e487d631330
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703978000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2703978000
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3475107270
Short name T809
Test name
Test status
Simulation time 27059320 ps
CPU time 0.79 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198488 kb
Host smart-604d3282-a0a5-42b7-8d62-e528c5f55318
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475107270 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3475107270
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3946479156
Short name T788
Test name
Test status
Simulation time 27697936 ps
CPU time 0.56 seconds
Started Aug 06 04:32:08 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 194568 kb
Host smart-3f9d6f38-be64-4208-8204-9597f67e059b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946479156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3946479156
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3823935832
Short name T728
Test name
Test status
Simulation time 20778837 ps
CPU time 0.64 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:08 PM PDT 24
Peak memory 194412 kb
Host smart-e234583a-3bac-40c0-99a7-c1dfafb16eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823935832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3823935832
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3195137441
Short name T828
Test name
Test status
Simulation time 83808403 ps
CPU time 0.63 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:06 PM PDT 24
Peak memory 195192 kb
Host smart-a722f18c-1794-4e8f-b6ba-0633dc717a22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195137441 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3195137441
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.342405099
Short name T842
Test name
Test status
Simulation time 221981501 ps
CPU time 1.63 seconds
Started Aug 06 04:32:07 PM PDT 24
Finished Aug 06 04:32:09 PM PDT 24
Peak memory 198640 kb
Host smart-73d78448-345a-410a-9733-4f2619fa4aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342405099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.342405099
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1923088696
Short name T28
Test name
Test status
Simulation time 80877073 ps
CPU time 1.17 seconds
Started Aug 06 04:32:06 PM PDT 24
Finished Aug 06 04:32:07 PM PDT 24
Peak memory 198608 kb
Host smart-a40b3754-eca6-4595-a25c-57b832329f1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923088696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1923088696
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3777954269
Short name T482
Test name
Test status
Simulation time 70629187 ps
CPU time 0.63 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 193120 kb
Host smart-f8d7b6ce-7370-4899-977a-6dd2e463a3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777954269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3777954269
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1952514958
Short name T535
Test name
Test status
Simulation time 188111735 ps
CPU time 1.03 seconds
Started Aug 06 04:33:12 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 197100 kb
Host smart-3620f44e-0e9a-4561-82ab-e2f654d47c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952514958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1952514958
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3535142488
Short name T274
Test name
Test status
Simulation time 1041329728 ps
CPU time 15.51 seconds
Started Aug 06 04:33:11 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 195948 kb
Host smart-a3ac170b-5238-4881-8ced-4e4a85f37140
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535142488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3535142488
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3100782490
Short name T393
Test name
Test status
Simulation time 75382936 ps
CPU time 1.08 seconds
Started Aug 06 04:33:13 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 197080 kb
Host smart-180634f2-8005-45cd-a2a6-99ce74610281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100782490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3100782490
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3516869347
Short name T688
Test name
Test status
Simulation time 162727985 ps
CPU time 1.28 seconds
Started Aug 06 04:33:12 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 197412 kb
Host smart-caa7773b-3265-4b43-88df-347363ed60c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516869347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3516869347
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2570995232
Short name T632
Test name
Test status
Simulation time 96332120 ps
CPU time 3.73 seconds
Started Aug 06 04:33:08 PM PDT 24
Finished Aug 06 04:33:12 PM PDT 24
Peak memory 198564 kb
Host smart-0584ee5e-c3bc-4fab-8c07-f3a3b5154494
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570995232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2570995232
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3450815584
Short name T330
Test name
Test status
Simulation time 86967841 ps
CPU time 1.03 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 195796 kb
Host smart-0a1be906-acbe-4c09-a623-36633d6de7d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450815584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3450815584
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2184262338
Short name T597
Test name
Test status
Simulation time 72097417 ps
CPU time 1.27 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 198388 kb
Host smart-914e89c3-066c-4deb-8181-d5e63e515ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184262338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2184262338
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.524768886
Short name T573
Test name
Test status
Simulation time 122901179 ps
CPU time 1.3 seconds
Started Aug 06 04:33:08 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 196280 kb
Host smart-24eb7e75-8170-4a37-ad81-d3ff54497ff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524768886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.524768886
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2660145447
Short name T484
Test name
Test status
Simulation time 334626023 ps
CPU time 2.75 seconds
Started Aug 06 04:33:11 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 198420 kb
Host smart-68694a9f-500f-4958-a7f9-52e283800188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660145447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2660145447
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1967482288
Short name T717
Test name
Test status
Simulation time 72492903 ps
CPU time 1.07 seconds
Started Aug 06 04:33:12 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 196096 kb
Host smart-b72d67ff-bb22-42ca-bba3-caf802b47124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967482288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1967482288
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2441297515
Short name T591
Test name
Test status
Simulation time 37140214 ps
CPU time 0.76 seconds
Started Aug 06 04:33:12 PM PDT 24
Finished Aug 06 04:33:13 PM PDT 24
Peak memory 195452 kb
Host smart-a8d34dac-e985-4818-b47e-67ebf3d1c3db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441297515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2441297515
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1162468818
Short name T474
Test name
Test status
Simulation time 4236474706 ps
CPU time 50.75 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:34:00 PM PDT 24
Peak memory 198608 kb
Host smart-d0bc8e3c-8168-4b3d-9f64-ee26e7baabc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162468818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1162468818
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2599071695
Short name T559
Test name
Test status
Simulation time 33337295 ps
CPU time 0.99 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:05 PM PDT 24
Peak memory 197132 kb
Host smart-d268f317-1d61-43e8-b81e-ff74de2baa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599071695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2599071695
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4099093944
Short name T546
Test name
Test status
Simulation time 619346177 ps
CPU time 7.31 seconds
Started Aug 06 04:33:02 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 198336 kb
Host smart-42809cc0-d4df-41e3-a21e-bc8dd6a75916
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099093944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4099093944
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1745463515
Short name T530
Test name
Test status
Simulation time 86732913 ps
CPU time 0.68 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 195340 kb
Host smart-129c4955-b387-48b6-8d89-eeae61ce583b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745463515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1745463515
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.782599074
Short name T656
Test name
Test status
Simulation time 33316326 ps
CPU time 0.8 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:03 PM PDT 24
Peak memory 195924 kb
Host smart-bba07453-b60f-46d6-b0bb-4dbe0f2ca1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782599074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.782599074
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2117598210
Short name T141
Test name
Test status
Simulation time 238518490 ps
CPU time 2.56 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 198392 kb
Host smart-e682e1e4-f79e-49af-b5b7-9607572157c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117598210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2117598210
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1112421786
Short name T284
Test name
Test status
Simulation time 472745960 ps
CPU time 2.44 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 197504 kb
Host smart-91ea77ac-9994-45d2-bb86-4e2ad3805a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112421786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1112421786
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3572117420
Short name T245
Test name
Test status
Simulation time 74063932 ps
CPU time 0.96 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 197084 kb
Host smart-6616d4b1-5be9-4506-bf09-4f8d41e20f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572117420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3572117420
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2436633622
Short name T285
Test name
Test status
Simulation time 127524713 ps
CPU time 0.78 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:05 PM PDT 24
Peak memory 196896 kb
Host smart-4a804e81-5412-44d7-aa41-4b291079096e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436633622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2436633622
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2931874962
Short name T8
Test name
Test status
Simulation time 330424714 ps
CPU time 3.87 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 198392 kb
Host smart-61d199a1-23c9-48ef-82d5-59ba714b3d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931874962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2931874962
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2401440802
Short name T42
Test name
Test status
Simulation time 89009157 ps
CPU time 0.86 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 214084 kb
Host smart-1c094484-49f0-40a8-a904-3966d64aabbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401440802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2401440802
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2864581810
Short name T15
Test name
Test status
Simulation time 261967134 ps
CPU time 1.27 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:05 PM PDT 24
Peak memory 197152 kb
Host smart-1dad4cd1-03e6-4184-b042-1d2d3dab9c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864581810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2864581810
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1147820684
Short name T74
Test name
Test status
Simulation time 126229300 ps
CPU time 0.87 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 195640 kb
Host smart-13254d29-4c36-4d0b-af9b-1bf2b04bd7da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147820684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1147820684
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3911045259
Short name T340
Test name
Test status
Simulation time 9383606861 ps
CPU time 56.5 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:34:02 PM PDT 24
Peak memory 198520 kb
Host smart-76bd6ef9-3378-4d29-8cad-c3b4fbfe504e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911045259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3911045259
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2596614769
Short name T377
Test name
Test status
Simulation time 16875767 ps
CPU time 0.56 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 194364 kb
Host smart-a7da0ad9-667c-453c-bffa-c87a19474ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596614769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2596614769
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.579363135
Short name T293
Test name
Test status
Simulation time 95448114 ps
CPU time 0.6 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 194920 kb
Host smart-87d897a4-44c3-43a6-827f-3d36170f16e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579363135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.579363135
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3073310115
Short name T115
Test name
Test status
Simulation time 3752876077 ps
CPU time 25.83 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:34:00 PM PDT 24
Peak memory 197088 kb
Host smart-aad6013e-1d12-4100-8adc-86a820318bd7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073310115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3073310115
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.228083859
Short name T481
Test name
Test status
Simulation time 85775959 ps
CPU time 0.93 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 198096 kb
Host smart-19aac23f-bcdb-4222-b51f-b9794fabe094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228083859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.228083859
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.221511413
Short name T610
Test name
Test status
Simulation time 25914625 ps
CPU time 0.64 seconds
Started Aug 06 04:33:32 PM PDT 24
Finished Aug 06 04:33:33 PM PDT 24
Peak memory 194648 kb
Host smart-70b8319c-a906-412d-a0c2-8e7e6f026c2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221511413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.221511413
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3780894844
Short name T476
Test name
Test status
Simulation time 182744843 ps
CPU time 2.51 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 198380 kb
Host smart-4badd3b9-f1c7-4c66-b2d6-5b6f536a50af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780894844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3780894844
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1142334631
Short name T294
Test name
Test status
Simulation time 72240490 ps
CPU time 1.05 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 196640 kb
Host smart-786902da-dc66-4b9b-8daf-b4d3ba589aed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142334631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1142334631
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3404317998
Short name T617
Test name
Test status
Simulation time 51134772 ps
CPU time 1.2 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 196440 kb
Host smart-9733a580-b27c-438e-8187-e4ec6dcb8138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404317998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3404317998
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2075247806
Short name T43
Test name
Test status
Simulation time 69906644 ps
CPU time 0.84 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 197192 kb
Host smart-06e9754b-6c98-480e-a625-efb58c8e28ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075247806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2075247806
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3147738231
Short name T259
Test name
Test status
Simulation time 543420584 ps
CPU time 3.3 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:30 PM PDT 24
Peak memory 198316 kb
Host smart-9298c4b3-ecd6-4e43-8cf7-57ab9f2c57ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147738231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3147738231
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2115689189
Short name T422
Test name
Test status
Simulation time 90357337 ps
CPU time 1.38 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:33:30 PM PDT 24
Peak memory 197012 kb
Host smart-027ec8f8-4392-4663-92fc-b6ba37b736a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115689189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2115689189
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1221530173
Short name T207
Test name
Test status
Simulation time 76807910 ps
CPU time 0.67 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:33:30 PM PDT 24
Peak memory 194372 kb
Host smart-184f2730-1932-4f6a-9ed9-65a9f4e38d62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221530173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1221530173
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2782638492
Short name T608
Test name
Test status
Simulation time 24600934464 ps
CPU time 164.13 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:36:17 PM PDT 24
Peak memory 198620 kb
Host smart-6a2f48d5-f276-4633-aa7f-7c41c28dde5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782638492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2782638492
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.48416176
Short name T650
Test name
Test status
Simulation time 26279249139 ps
CPU time 688.48 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:44:58 PM PDT 24
Peak memory 198796 kb
Host smart-f0bf6fe2-2767-498c-b79b-5678a0784af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=48416176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.48416176
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3795982988
Short name T68
Test name
Test status
Simulation time 37921392 ps
CPU time 0.55 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 194492 kb
Host smart-f5da468f-de6c-4eb9-9eed-9eedb6c7519d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795982988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3795982988
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.340647853
Short name T63
Test name
Test status
Simulation time 117606699 ps
CPU time 0.73 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 196360 kb
Host smart-bf36a6c5-47b6-44ab-985d-75f6cdbef1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340647853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.340647853
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2289148606
Short name T531
Test name
Test status
Simulation time 188616758 ps
CPU time 9.52 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:41 PM PDT 24
Peak memory 197032 kb
Host smart-cd78377b-ce0c-4766-953f-507242cd43c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289148606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2289148606
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2095138980
Short name T276
Test name
Test status
Simulation time 81212764 ps
CPU time 0.77 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 196012 kb
Host smart-006c5281-f430-4a1e-9601-534c6c73d012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095138980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2095138980
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2072609468
Short name T383
Test name
Test status
Simulation time 197079076 ps
CPU time 0.93 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 196208 kb
Host smart-b3f4ef88-b86d-4a97-8c22-100fd1472cac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072609468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2072609468
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2679825686
Short name T204
Test name
Test status
Simulation time 109443179 ps
CPU time 1.27 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 198576 kb
Host smart-413ba645-c620-4d5f-824a-3e906c4a2af1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679825686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2679825686
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.797674626
Short name T358
Test name
Test status
Simulation time 75074423 ps
CPU time 1.98 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 197444 kb
Host smart-bfada13d-6532-4f68-b8a7-9be68fa6c587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797674626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
797674626
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1177053647
Short name T249
Test name
Test status
Simulation time 29065068 ps
CPU time 0.73 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 196488 kb
Host smart-d872498a-f0aa-41b2-93e1-997eb50351b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177053647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1177053647
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4085730290
Short name T402
Test name
Test status
Simulation time 134966980 ps
CPU time 0.82 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196208 kb
Host smart-43a756a1-f41d-437e-bd8b-e9ff469aaa18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085730290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4085730290
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3478777570
Short name T122
Test name
Test status
Simulation time 285760744 ps
CPU time 4.58 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 198512 kb
Host smart-399c9cd4-ed3f-4bc3-81f0-1ee478238f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478777570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3478777570
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3703545775
Short name T430
Test name
Test status
Simulation time 93764741 ps
CPU time 0.9 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 196168 kb
Host smart-62021839-7ad1-4fbd-89a5-75cc7bc8bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703545775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3703545775
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.791762026
Short name T601
Test name
Test status
Simulation time 44723127 ps
CPU time 0.96 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 196892 kb
Host smart-182e85c4-3167-4efb-a613-c5daaa168294
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791762026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.791762026
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2003954776
Short name T246
Test name
Test status
Simulation time 14356718232 ps
CPU time 208.43 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:36:57 PM PDT 24
Peak memory 198584 kb
Host smart-973ecfd0-0681-4074-8b24-225f8d8395a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003954776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2003954776
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3093550692
Short name T492
Test name
Test status
Simulation time 13178960 ps
CPU time 0.57 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 194308 kb
Host smart-df0cb069-b90c-4ce2-bf77-23c50d327105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093550692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3093550692
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4164418748
Short name T146
Test name
Test status
Simulation time 38230474 ps
CPU time 0.9 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 197612 kb
Host smart-cb5913f5-0f51-4f2b-a4a6-9ab94a4d4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164418748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4164418748
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.492860563
Short name T127
Test name
Test status
Simulation time 1635119317 ps
CPU time 10.19 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 197364 kb
Host smart-d889f6aa-890b-480a-b51e-ed4612b4b773
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492860563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.492860563
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3300026778
Short name T447
Test name
Test status
Simulation time 43748781 ps
CPU time 0.65 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 195092 kb
Host smart-a76ad2c8-2139-4fb3-8f3d-c79557ccfa2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300026778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3300026778
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2255861940
Short name T254
Test name
Test status
Simulation time 77882859 ps
CPU time 1.13 seconds
Started Aug 06 04:33:32 PM PDT 24
Finished Aug 06 04:33:33 PM PDT 24
Peak memory 196608 kb
Host smart-f34cf237-4e73-45bb-95de-08bf6c163e3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255861940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2255861940
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.244516052
Short name T452
Test name
Test status
Simulation time 40637070 ps
CPU time 1.56 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 198388 kb
Host smart-a5b43d61-46f5-443d-b96e-aef886cefbf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244516052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.244516052
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2832270110
Short name T558
Test name
Test status
Simulation time 73296996 ps
CPU time 1.57 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196544 kb
Host smart-e1e85c84-5b13-4c69-aa2b-f6465d12ff35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832270110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2832270110
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4190052512
Short name T442
Test name
Test status
Simulation time 51472256 ps
CPU time 0.95 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:33:30 PM PDT 24
Peak memory 196332 kb
Host smart-091b6604-6def-4586-a5cc-2534d26f349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190052512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4190052512
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3249057641
Short name T212
Test name
Test status
Simulation time 36709299 ps
CPU time 0.73 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 196500 kb
Host smart-790b6f4a-0804-48d1-8982-b4a4e67b23bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249057641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3249057641
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1112488466
Short name T406
Test name
Test status
Simulation time 294837995 ps
CPU time 3.81 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 198508 kb
Host smart-8a81dcfb-e716-4199-b945-a71a01115c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112488466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1112488466
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4085682478
Short name T123
Test name
Test status
Simulation time 217335341 ps
CPU time 1.04 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 196744 kb
Host smart-8306bbe0-dbb5-41ee-9fe1-35bc8dc6cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085682478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4085682478
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1418833694
Short name T396
Test name
Test status
Simulation time 54264891 ps
CPU time 0.76 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 195484 kb
Host smart-b0c24fc8-8553-454a-950d-6c755fdc9c9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418833694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1418833694
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3893844514
Short name T427
Test name
Test status
Simulation time 21066495913 ps
CPU time 72.65 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:34:42 PM PDT 24
Peak memory 198484 kb
Host smart-c79e2369-8130-47e3-b126-f6f3b56feae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893844514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3893844514
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1647511910
Short name T56
Test name
Test status
Simulation time 51449683744 ps
CPU time 1440.77 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:57:36 PM PDT 24
Peak memory 198836 kb
Host smart-272ddd1c-ca94-4e54-be60-e8e657aa95ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1647511910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1647511910
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2184805366
Short name T525
Test name
Test status
Simulation time 58699987 ps
CPU time 0.58 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 194284 kb
Host smart-c5604842-90e2-4a87-b393-7b5a081ea15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184805366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2184805366
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.703855916
Short name T22
Test name
Test status
Simulation time 54594106 ps
CPU time 1 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 196412 kb
Host smart-946c919e-c8cc-4576-84b7-1cdf81e96902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703855916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.703855916
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.712837960
Short name T572
Test name
Test status
Simulation time 309884748 ps
CPU time 8.27 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 198464 kb
Host smart-e39194e0-9d09-49b0-a974-c33f91a632d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712837960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.712837960
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3814430754
Short name T3
Test name
Test status
Simulation time 870977592 ps
CPU time 1.06 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:36 PM PDT 24
Peak memory 196984 kb
Host smart-fda234fc-2fb1-4eb4-8b5e-84afd31ff1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814430754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3814430754
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3042768019
Short name T689
Test name
Test status
Simulation time 80890859 ps
CPU time 1.14 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 196568 kb
Host smart-007420f6-bfb7-49cc-bbc9-ddc3df46c67e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042768019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3042768019
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.347930747
Short name T234
Test name
Test status
Simulation time 90859571 ps
CPU time 1.98 seconds
Started Aug 06 04:33:32 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 198428 kb
Host smart-4cdc15ea-44fa-4484-aeee-3a1d98c7539d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347930747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.347930747
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3823872897
Short name T227
Test name
Test status
Simulation time 1668119146 ps
CPU time 2.68 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:36 PM PDT 24
Peak memory 196272 kb
Host smart-5ab11570-e780-431f-ae56-b5082cede978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823872897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3823872897
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.989059041
Short name T350
Test name
Test status
Simulation time 28797774 ps
CPU time 1.08 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:36 PM PDT 24
Peak memory 196364 kb
Host smart-db11ae80-5646-41b3-b5dc-a2c82ed47962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989059041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.989059041
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2567453148
Short name T418
Test name
Test status
Simulation time 38844252 ps
CPU time 0.83 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 196260 kb
Host smart-2a06b362-1f28-411a-9589-4b298904cd08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567453148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2567453148
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2091923377
Short name T247
Test name
Test status
Simulation time 245952216 ps
CPU time 2.67 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 198472 kb
Host smart-f174be8a-eff1-4504-912a-67ac1a4076a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091923377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2091923377
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4096905321
Short name T217
Test name
Test status
Simulation time 72235328 ps
CPU time 1.2 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196880 kb
Host smart-1d2d6603-5fff-401b-9011-1d4bc756e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096905321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4096905321
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1184662266
Short name T555
Test name
Test status
Simulation time 738931530 ps
CPU time 1.09 seconds
Started Aug 06 04:33:32 PM PDT 24
Finished Aug 06 04:33:33 PM PDT 24
Peak memory 195980 kb
Host smart-5f2a2ada-816c-4821-a7a1-56ff13a73248
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184662266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1184662266
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2431919698
Short name T421
Test name
Test status
Simulation time 99383984659 ps
CPU time 255.32 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:37:49 PM PDT 24
Peak memory 198568 kb
Host smart-ec04407e-195a-47be-8ef6-01185650ad75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431919698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2431919698
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1635496065
Short name T296
Test name
Test status
Simulation time 15680770 ps
CPU time 0.58 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 194492 kb
Host smart-983a516c-0323-446f-aaf8-b44bb86980e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635496065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1635496065
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4041178395
Short name T210
Test name
Test status
Simulation time 25946341 ps
CPU time 0.8 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196444 kb
Host smart-fad13c85-914a-4217-bf7e-0194d3f576c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041178395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4041178395
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3664015021
Short name T170
Test name
Test status
Simulation time 1791834489 ps
CPU time 5.56 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 197120 kb
Host smart-34eecfa0-a36f-437d-ae38-a4078b1f476d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664015021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3664015021
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2783612066
Short name T506
Test name
Test status
Simulation time 38386042 ps
CPU time 0.59 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 194800 kb
Host smart-67f781a4-63a3-4bbb-9449-21c62db1506f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783612066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2783612066
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.117199470
Short name T138
Test name
Test status
Simulation time 466082248 ps
CPU time 1.26 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:37 PM PDT 24
Peak memory 196988 kb
Host smart-f7285db4-9fe4-419d-92ba-713c57f5ccdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117199470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.117199470
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.458716992
Short name T168
Test name
Test status
Simulation time 44034367 ps
CPU time 1.73 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 197064 kb
Host smart-15b8ede6-7dec-44c3-813b-0462abe0154b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458716992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.458716992
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3297482197
Short name T692
Test name
Test status
Simulation time 156953499 ps
CPU time 1.63 seconds
Started Aug 06 04:33:40 PM PDT 24
Finished Aug 06 04:33:42 PM PDT 24
Peak memory 196036 kb
Host smart-f3ffbd5d-dcde-4fcd-ae02-d6e3fefef016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297482197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3297482197
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2258446931
Short name T516
Test name
Test status
Simulation time 34135960 ps
CPU time 1.1 seconds
Started Aug 06 04:33:40 PM PDT 24
Finished Aug 06 04:33:41 PM PDT 24
Peak memory 197228 kb
Host smart-20f5db03-b3e0-4b32-98b5-92258ce937ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258446931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2258446931
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1728625648
Short name T444
Test name
Test status
Simulation time 254835315 ps
CPU time 1.22 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 197404 kb
Host smart-b9a1eed5-e0bc-44ff-aa18-f3bab16f566d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728625648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1728625648
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.821896888
Short name T371
Test name
Test status
Simulation time 1999273856 ps
CPU time 5.65 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 198360 kb
Host smart-617636af-8f65-4b4d-a942-b3e1c4e33e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821896888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.821896888
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2798473663
Short name T60
Test name
Test status
Simulation time 53772280 ps
CPU time 1.05 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 195964 kb
Host smart-432de419-7e08-4f7e-a59d-549783dd4bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798473663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2798473663
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1531534816
Short name T678
Test name
Test status
Simulation time 266081686 ps
CPU time 1.25 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 197112 kb
Host smart-abda3f60-be0e-46ab-95f7-1e4453351932
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531534816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1531534816
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2214914358
Short name T423
Test name
Test status
Simulation time 57526517647 ps
CPU time 150.69 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:36:06 PM PDT 24
Peak memory 192444 kb
Host smart-50c853b2-bc8c-481c-b2d1-9e7f4809ef1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214914358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2214914358
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3333660025
Short name T77
Test name
Test status
Simulation time 137335227335 ps
CPU time 1680.24 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 05:01:38 PM PDT 24
Peak memory 198764 kb
Host smart-352e249e-97e8-4caf-a6c9-d6843feb6f37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3333660025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3333660025
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3320816741
Short name T269
Test name
Test status
Simulation time 12945157 ps
CPU time 0.58 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 194356 kb
Host smart-02c64545-bb3a-40f5-9f58-94d50cdc96b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320816741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3320816741
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.509551238
Short name T681
Test name
Test status
Simulation time 51587992 ps
CPU time 0.64 seconds
Started Aug 06 04:33:40 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 194420 kb
Host smart-f92eddc3-555a-47d7-b74b-2eb550df5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509551238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.509551238
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.214335592
Short name T184
Test name
Test status
Simulation time 1352256014 ps
CPU time 9.35 seconds
Started Aug 06 04:33:47 PM PDT 24
Finished Aug 06 04:33:57 PM PDT 24
Peak memory 197280 kb
Host smart-5399e042-e110-4ce9-a81f-2730121e2b2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214335592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.214335592
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2709526130
Short name T712
Test name
Test status
Simulation time 124868990 ps
CPU time 0.82 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 196236 kb
Host smart-314664fd-ba55-48d1-9c25-1e8043d008ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709526130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2709526130
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3303393011
Short name T178
Test name
Test status
Simulation time 88647643 ps
CPU time 1.18 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 196420 kb
Host smart-fabf7977-da35-4cfa-87b2-49cff547f482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303393011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3303393011
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3513742931
Short name T150
Test name
Test status
Simulation time 301966833 ps
CPU time 1.76 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 198632 kb
Host smart-f411ae70-de8b-4d68-b6be-4a5427ceb81f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513742931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3513742931
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2508080953
Short name T182
Test name
Test status
Simulation time 153477788 ps
CPU time 1.14 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 196204 kb
Host smart-f1ddfc65-72a1-42bf-805f-6e0a5da576f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508080953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2508080953
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2077830064
Short name T620
Test name
Test status
Simulation time 149811722 ps
CPU time 1.11 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 196972 kb
Host smart-81312d8e-7cf7-43a3-a740-1f37e7d02237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077830064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2077830064
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3089103565
Short name T571
Test name
Test status
Simulation time 63922250 ps
CPU time 0.69 seconds
Started Aug 06 04:33:41 PM PDT 24
Finished Aug 06 04:33:41 PM PDT 24
Peak memory 194644 kb
Host smart-ccf3a383-4562-4b63-8c73-7e806c086028
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089103565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3089103565
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1896484577
Short name T271
Test name
Test status
Simulation time 6176904910 ps
CPU time 3.9 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 198584 kb
Host smart-45af4a05-d504-4d2a-8f04-a4002c22ae11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896484577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1896484577
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3377431044
Short name T537
Test name
Test status
Simulation time 80576993 ps
CPU time 1.36 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 197272 kb
Host smart-fa4d8bf2-fac1-40f5-9e35-66990158518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377431044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3377431044
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3285511293
Short name T661
Test name
Test status
Simulation time 134925427 ps
CPU time 1.23 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 196852 kb
Host smart-40093235-6edf-40b4-af91-1c93b2f4b45b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285511293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3285511293
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.767425005
Short name T135
Test name
Test status
Simulation time 5197789454 ps
CPU time 115.84 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:35:35 PM PDT 24
Peak memory 198472 kb
Host smart-9c984b14-ef68-4214-974d-899cf0851ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767425005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.767425005
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3476817487
Short name T359
Test name
Test status
Simulation time 18607254 ps
CPU time 0.55 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 194320 kb
Host smart-c3b3ae5a-6239-4a55-b602-1fbf050186cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476817487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3476817487
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1810566749
Short name T225
Test name
Test status
Simulation time 62452129 ps
CPU time 0.66 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 195276 kb
Host smart-6bf93eb2-40bf-4f71-90a6-867e309789fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810566749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1810566749
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1705502636
Short name T589
Test name
Test status
Simulation time 415579171 ps
CPU time 6.29 seconds
Started Aug 06 04:33:49 PM PDT 24
Finished Aug 06 04:33:55 PM PDT 24
Peak memory 197356 kb
Host smart-5d83464d-3570-4e8c-87cc-87aedd313c87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705502636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1705502636
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2677246309
Short name T551
Test name
Test status
Simulation time 293711454 ps
CPU time 0.89 seconds
Started Aug 06 04:33:53 PM PDT 24
Finished Aug 06 04:33:54 PM PDT 24
Peak memory 197056 kb
Host smart-cd9ac5a0-3b46-498d-b618-a3d638127bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677246309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2677246309
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1911821399
Short name T116
Test name
Test status
Simulation time 1243130303 ps
CPU time 1.13 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 196344 kb
Host smart-bcf523fa-e0c4-41a1-97ba-0fad1cd1021d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911821399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1911821399
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3749628995
Short name T105
Test name
Test status
Simulation time 149653717 ps
CPU time 1.4 seconds
Started Aug 06 04:33:54 PM PDT 24
Finished Aug 06 04:33:55 PM PDT 24
Peak memory 196684 kb
Host smart-e5a33aed-83a1-4d41-89ef-f74bc3eb017b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749628995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3749628995
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.777793959
Short name T177
Test name
Test status
Simulation time 282881310 ps
CPU time 1.77 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 197124 kb
Host smart-179a4084-17e6-4753-9a9d-3f3fd7595681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777793959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
777793959
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4045444577
Short name T461
Test name
Test status
Simulation time 609526490 ps
CPU time 0.98 seconds
Started Aug 06 04:33:41 PM PDT 24
Finished Aug 06 04:33:42 PM PDT 24
Peak memory 196480 kb
Host smart-3ce44155-161e-469b-b7d8-6fccfb94e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045444577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4045444577
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3297554202
Short name T361
Test name
Test status
Simulation time 68419057 ps
CPU time 1.23 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 197400 kb
Host smart-b27f8f02-b83f-43eb-b06f-cfd29c093bb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297554202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3297554202
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1118076527
Short name T686
Test name
Test status
Simulation time 38477025 ps
CPU time 1.67 seconds
Started Aug 06 04:33:54 PM PDT 24
Finished Aug 06 04:33:56 PM PDT 24
Peak memory 198344 kb
Host smart-d3bd6105-db60-4d78-8502-266414eff28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118076527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1118076527
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4036740265
Short name T49
Test name
Test status
Simulation time 23242577 ps
CPU time 0.76 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 196416 kb
Host smart-79640ebe-86db-4d70-a74a-48970b3d920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036740265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4036740265
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3724284388
Short name T616
Test name
Test status
Simulation time 27366948 ps
CPU time 0.82 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 196468 kb
Host smart-7c373fe5-b44f-4dd8-b74d-1275c77cb315
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724284388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3724284388
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.41086934
Short name T329
Test name
Test status
Simulation time 1751359214 ps
CPU time 45.63 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 198456 kb
Host smart-7adc2163-bd27-4947-b8c7-34e25006818c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41086934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gp
io_stress_all.41086934
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1626552923
Short name T243
Test name
Test status
Simulation time 40796715 ps
CPU time 0.56 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 194284 kb
Host smart-f636b187-bee3-4d07-a590-79e87d20a06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626552923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1626552923
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1240898831
Short name T500
Test name
Test status
Simulation time 91183555 ps
CPU time 0.67 seconds
Started Aug 06 04:33:32 PM PDT 24
Finished Aug 06 04:33:33 PM PDT 24
Peak memory 195256 kb
Host smart-6d9c6620-9810-4706-92bc-731869e20ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240898831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1240898831
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3164461416
Short name T287
Test name
Test status
Simulation time 511039649 ps
CPU time 25.28 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:34:01 PM PDT 24
Peak memory 197184 kb
Host smart-f3778c68-0c19-4aca-ac27-1d5fb96c8cb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164461416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3164461416
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3428096640
Short name T224
Test name
Test status
Simulation time 281289554 ps
CPU time 0.92 seconds
Started Aug 06 04:33:35 PM PDT 24
Finished Aug 06 04:33:36 PM PDT 24
Peak memory 196944 kb
Host smart-84a92b29-d672-4962-8eb1-75077fa41da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428096640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3428096640
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1660915357
Short name T704
Test name
Test status
Simulation time 147236035 ps
CPU time 1.02 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196396 kb
Host smart-b663421a-e8d2-4c30-8d92-691420b691b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660915357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1660915357
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1135561228
Short name T485
Test name
Test status
Simulation time 29738030 ps
CPU time 1.27 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 198480 kb
Host smart-c3b6d27e-1601-4b35-ae82-f536cee1ef52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135561228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1135561228
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1427516786
Short name T159
Test name
Test status
Simulation time 72280634 ps
CPU time 1.66 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 197076 kb
Host smart-de724a54-45da-4e2a-b474-4e3ab27ce1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427516786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1427516786
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1857735654
Short name T201
Test name
Test status
Simulation time 297688857 ps
CPU time 1.12 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 197360 kb
Host smart-1f036cc7-26f5-4acc-bda7-1d8a9c890bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857735654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1857735654
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.716968387
Short name T102
Test name
Test status
Simulation time 32704524 ps
CPU time 1.21 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 197432 kb
Host smart-168493ab-e832-43c6-947c-2dc88e885ae1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716968387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.716968387
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2223756952
Short name T566
Test name
Test status
Simulation time 363609835 ps
CPU time 1.86 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 198352 kb
Host smart-1dc781de-bb93-4ebd-a63f-7e28cb069915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223756952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2223756952
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1726904422
Short name T129
Test name
Test status
Simulation time 38710032 ps
CPU time 0.8 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 195580 kb
Host smart-4bb1e699-d180-437a-9464-8fa39490d22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726904422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1726904422
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1263724577
Short name T528
Test name
Test status
Simulation time 58138208 ps
CPU time 0.7 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 194424 kb
Host smart-e14a86c3-dfc0-47e4-9349-fd015e89391b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263724577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1263724577
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2603264557
Short name T11
Test name
Test status
Simulation time 13569629431 ps
CPU time 101.37 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:35:20 PM PDT 24
Peak memory 198464 kb
Host smart-9c234f20-11d5-44b7-9e6b-f8682b277f02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603264557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2603264557
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2160733137
Short name T694
Test name
Test status
Simulation time 41257623403 ps
CPU time 1116.05 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:52:12 PM PDT 24
Peak memory 198676 kb
Host smart-e428df80-06bb-4fe6-adae-c21fbeedc38d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2160733137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2160733137
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.328801734
Short name T590
Test name
Test status
Simulation time 26577195 ps
CPU time 0.62 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 195252 kb
Host smart-d85a620c-04ad-4851-b1a7-7a6f9e761a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328801734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.328801734
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1321392917
Short name T576
Test name
Test status
Simulation time 32602767 ps
CPU time 0.75 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 195728 kb
Host smart-f0a0510f-b7d7-464c-b254-c0f246eb0a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321392917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1321392917
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2477252592
Short name T239
Test name
Test status
Simulation time 565684198 ps
CPU time 6.98 seconds
Started Aug 06 04:33:40 PM PDT 24
Finished Aug 06 04:33:47 PM PDT 24
Peak memory 197292 kb
Host smart-0202f3fe-b5ef-4a9d-a2b6-b07844121250
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477252592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2477252592
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.936030272
Short name T519
Test name
Test status
Simulation time 158356199 ps
CPU time 0.76 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 196384 kb
Host smart-fe00389b-1f15-4174-8e53-161e9ca5051f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936030272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.936030272
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4226233626
Short name T526
Test name
Test status
Simulation time 128024515 ps
CPU time 0.94 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 196360 kb
Host smart-9abdefe2-a725-446e-8f80-593a47f8112d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226233626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4226233626
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2723220296
Short name T295
Test name
Test status
Simulation time 348332679 ps
CPU time 3.07 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 198512 kb
Host smart-32127352-62ff-49a6-9343-02a70c39354a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723220296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2723220296
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4283136848
Short name T708
Test name
Test status
Simulation time 40112418 ps
CPU time 1.01 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 195792 kb
Host smart-e61016c2-6024-4959-9f5e-d2cd6c4a961f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283136848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4283136848
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2883420339
Short name T568
Test name
Test status
Simulation time 26400213 ps
CPU time 0.79 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 196600 kb
Host smart-c72b5977-c40c-4cb9-ab32-36471bcb631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883420339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2883420339
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1135611010
Short name T502
Test name
Test status
Simulation time 398108122 ps
CPU time 1.16 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 197356 kb
Host smart-e14def52-b409-4c56-872a-64ba99cc01cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135611010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1135611010
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2491223288
Short name T339
Test name
Test status
Simulation time 953856265 ps
CPU time 5.79 seconds
Started Aug 06 04:33:28 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 198444 kb
Host smart-58aba7cb-c618-4cc2-a365-24c37caafea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491223288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2491223288
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1972855715
Short name T675
Test name
Test status
Simulation time 93865347 ps
CPU time 0.83 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 196364 kb
Host smart-2d5d2539-c21a-4cb4-a06e-fda963d52965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972855715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1972855715
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2387780818
Short name T175
Test name
Test status
Simulation time 344532672 ps
CPU time 1.34 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 197220 kb
Host smart-e9af2e5e-8057-4258-b2f8-2dd3cc0654a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387780818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2387780818
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3431129990
Short name T645
Test name
Test status
Simulation time 10506625703 ps
CPU time 71.18 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 198624 kb
Host smart-74bb8da9-a40d-4b99-8196-52cbc10652a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431129990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3431129990
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2099008777
Short name T478
Test name
Test status
Simulation time 116676975997 ps
CPU time 2457.07 seconds
Started Aug 06 04:33:51 PM PDT 24
Finished Aug 06 05:14:48 PM PDT 24
Peak memory 198748 kb
Host smart-21cbc79f-aad2-4668-99b4-b8072313938f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2099008777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2099008777
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.561273182
Short name T630
Test name
Test status
Simulation time 21295755 ps
CPU time 0.55 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 194296 kb
Host smart-60375f90-fc76-4040-9eec-c075b55627d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561273182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.561273182
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.203878553
Short name T469
Test name
Test status
Simulation time 39815495 ps
CPU time 0.66 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 193848 kb
Host smart-6733b49c-b6ca-45f0-aa6c-7747debc2bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203878553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.203878553
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2708116943
Short name T679
Test name
Test status
Simulation time 407996642 ps
CPU time 19.2 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:58 PM PDT 24
Peak memory 198244 kb
Host smart-eb275b85-a7ac-4e0d-a2d1-ed7275592f09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708116943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2708116943
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.323292669
Short name T12
Test name
Test status
Simulation time 29178708 ps
CPU time 0.68 seconds
Started Aug 06 04:33:40 PM PDT 24
Finished Aug 06 04:33:41 PM PDT 24
Peak memory 195764 kb
Host smart-1d082b5b-1753-43f4-97c3-7d24b2223bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323292669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.323292669
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1958697210
Short name T475
Test name
Test status
Simulation time 25079733 ps
CPU time 0.81 seconds
Started Aug 06 04:33:30 PM PDT 24
Finished Aug 06 04:33:31 PM PDT 24
Peak memory 195160 kb
Host smart-a5556060-4e34-408a-8456-307f67ce78b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958697210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1958697210
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.390691569
Short name T647
Test name
Test status
Simulation time 89930516 ps
CPU time 3.47 seconds
Started Aug 06 04:33:49 PM PDT 24
Finished Aug 06 04:33:53 PM PDT 24
Peak memory 198440 kb
Host smart-cfc9e3c5-136d-4728-97bc-c5e91e478f01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390691569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.390691569
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.136565341
Short name T233
Test name
Test status
Simulation time 42616112 ps
CPU time 1.11 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 196140 kb
Host smart-a4206c96-b8ff-44c8-bc8e-2a5b7406efc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136565341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
136565341
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.397486609
Short name T367
Test name
Test status
Simulation time 102869799 ps
CPU time 1.12 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 197120 kb
Host smart-1907e4dd-6991-4afa-9e8e-500d47fb9b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397486609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.397486609
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1143338113
Short name T124
Test name
Test status
Simulation time 30533961 ps
CPU time 0.81 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 195620 kb
Host smart-dc40703c-1e0d-48da-ae14-c3bf0f750d8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143338113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1143338113
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3720464180
Short name T676
Test name
Test status
Simulation time 242524585 ps
CPU time 5.38 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 198296 kb
Host smart-ebc20921-09fe-4cc6-ad75-8b5b25da94b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720464180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3720464180
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1137422305
Short name T362
Test name
Test status
Simulation time 71032975 ps
CPU time 1.07 seconds
Started Aug 06 04:33:37 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 196156 kb
Host smart-d2331dd0-c63d-46c0-9c65-f184bcb2b9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137422305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1137422305
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1951563050
Short name T624
Test name
Test status
Simulation time 604694317 ps
CPU time 1.14 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:33:40 PM PDT 24
Peak memory 197312 kb
Host smart-14cf12f5-310d-4c12-a236-909c062641d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951563050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1951563050
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3717965559
Short name T4
Test name
Test status
Simulation time 42941188067 ps
CPU time 120.51 seconds
Started Aug 06 04:33:39 PM PDT 24
Finished Aug 06 04:35:40 PM PDT 24
Peak memory 198488 kb
Host smart-cf0761ab-a8db-49a6-aad8-8600afe4bebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717965559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3717965559
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1998672782
Short name T25
Test name
Test status
Simulation time 125196319349 ps
CPU time 1437.37 seconds
Started Aug 06 04:33:47 PM PDT 24
Finished Aug 06 04:57:44 PM PDT 24
Peak memory 198784 kb
Host smart-25496034-b0e7-4a7f-bfce-e219fa003342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1998672782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1998672782
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1117703581
Short name T570
Test name
Test status
Simulation time 21001466 ps
CPU time 0.61 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 194128 kb
Host smart-4b74d6b9-4d8d-4f06-8904-055604fc905a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117703581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1117703581
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3227746999
Short name T197
Test name
Test status
Simulation time 275363434 ps
CPU time 0.88 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:11 PM PDT 24
Peak memory 196412 kb
Host smart-b797c80b-ac57-47d6-98cc-87f8cd144f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227746999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3227746999
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1505644984
Short name T603
Test name
Test status
Simulation time 5751494959 ps
CPU time 26.64 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 197224 kb
Host smart-1747739b-2447-42a6-b427-0b7b18284190
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505644984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1505644984
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1307861690
Short name T303
Test name
Test status
Simulation time 105388290 ps
CPU time 0.73 seconds
Started Aug 06 04:33:08 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 195168 kb
Host smart-08382b29-5966-4d6d-be69-5b05d14e7b91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307861690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1307861690
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2438032281
Short name T158
Test name
Test status
Simulation time 49678738 ps
CPU time 0.9 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 195900 kb
Host smart-ba0fb0de-d0af-4db7-87d3-ff7095ea5d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438032281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2438032281
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3924510598
Short name T251
Test name
Test status
Simulation time 94644338 ps
CPU time 3.48 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 198408 kb
Host smart-bb0c6fb7-96fd-43f8-87ab-5b65ecbc3c62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924510598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3924510598
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.571302901
Short name T67
Test name
Test status
Simulation time 123230665 ps
CPU time 2.58 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 198492 kb
Host smart-e437c063-d18a-4e63-9408-b3c511af0af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571302901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.571302901
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2390382492
Short name T308
Test name
Test status
Simulation time 103759903 ps
CPU time 0.68 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 194624 kb
Host smart-94092937-fe3c-43dd-8cba-83b73c2b00f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390382492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2390382492
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.611024127
Short name T61
Test name
Test status
Simulation time 38351827 ps
CPU time 0.91 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 196880 kb
Host smart-b7809fd9-c85d-479d-a3ba-ba6e82b3636c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611024127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.611024127
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1954698645
Short name T376
Test name
Test status
Simulation time 183877532 ps
CPU time 2.07 seconds
Started Aug 06 04:33:08 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 198272 kb
Host smart-73f0369a-a0d2-401d-a572-3b63e2adf807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954698645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1954698645
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.930341511
Short name T31
Test name
Test status
Simulation time 90565577 ps
CPU time 0.99 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:11 PM PDT 24
Peak memory 215260 kb
Host smart-72cd6df2-2b54-4773-b27b-ba90c186cf9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930341511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.930341511
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2901426291
Short name T317
Test name
Test status
Simulation time 39975939 ps
CPU time 1.18 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 197220 kb
Host smart-28a5f60a-4da4-447a-8b5f-01be3c310395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901426291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2901426291
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2158706596
Short name T556
Test name
Test status
Simulation time 90461830 ps
CPU time 1.45 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 197232 kb
Host smart-b6621ceb-c40e-4d50-a8ef-ad0f2783e0d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158706596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2158706596
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4261202864
Short name T609
Test name
Test status
Simulation time 18686844836 ps
CPU time 220.43 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:36:46 PM PDT 24
Peak memory 198612 kb
Host smart-762a85c3-b433-496c-8725-d6451f6508f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261202864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4261202864
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4065882565
Short name T646
Test name
Test status
Simulation time 40515453 ps
CPU time 0.57 seconds
Started Aug 06 04:33:53 PM PDT 24
Finished Aug 06 04:33:53 PM PDT 24
Peak memory 194300 kb
Host smart-e16d72b6-1479-444c-ab26-9468be312a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065882565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4065882565
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2730559231
Short name T716
Test name
Test status
Simulation time 81033430 ps
CPU time 0.74 seconds
Started Aug 06 04:33:46 PM PDT 24
Finished Aug 06 04:33:47 PM PDT 24
Peak memory 195568 kb
Host smart-a90a77d9-14b1-4734-948a-6a6861febf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730559231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2730559231
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.742798229
Short name T75
Test name
Test status
Simulation time 572964401 ps
CPU time 18.13 seconds
Started Aug 06 04:33:47 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 197248 kb
Host smart-87850755-d61a-438e-8078-9273aee1ab22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742798229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.742798229
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.405297283
Short name T415
Test name
Test status
Simulation time 191266477 ps
CPU time 1 seconds
Started Aug 06 04:33:53 PM PDT 24
Finished Aug 06 04:33:54 PM PDT 24
Peak memory 196808 kb
Host smart-a4698906-045b-40af-a97f-16c588702aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405297283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.405297283
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2561330920
Short name T654
Test name
Test status
Simulation time 105082456 ps
CPU time 0.95 seconds
Started Aug 06 04:33:54 PM PDT 24
Finished Aug 06 04:33:55 PM PDT 24
Peak memory 197136 kb
Host smart-b5b1a796-ff18-4816-9308-8f0d9a2f6181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561330920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2561330920
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3143302524
Short name T352
Test name
Test status
Simulation time 50099531 ps
CPU time 1.92 seconds
Started Aug 06 04:33:41 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 198460 kb
Host smart-cf0e1b42-d74a-4824-9be5-ae6ea7681a0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143302524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3143302524
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3773488619
Short name T351
Test name
Test status
Simulation time 27973594 ps
CPU time 0.84 seconds
Started Aug 06 04:33:59 PM PDT 24
Finished Aug 06 04:34:00 PM PDT 24
Peak memory 195416 kb
Host smart-1014d0b4-b297-4d96-9553-6bccbcb016f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773488619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3773488619
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1592595550
Short name T462
Test name
Test status
Simulation time 56971167 ps
CPU time 0.82 seconds
Started Aug 06 04:33:38 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 196756 kb
Host smart-e13f2f17-3df9-459d-8a50-a792bfb1e3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592595550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1592595550
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1194768731
Short name T188
Test name
Test status
Simulation time 245582920 ps
CPU time 1.03 seconds
Started Aug 06 04:33:41 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 196464 kb
Host smart-f43a5989-9af9-4851-842d-fc306b60568a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194768731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1194768731
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.4045794494
Short name T322
Test name
Test status
Simulation time 839735079 ps
CPU time 2.78 seconds
Started Aug 06 04:33:49 PM PDT 24
Finished Aug 06 04:33:52 PM PDT 24
Peak memory 198252 kb
Host smart-31bcebbd-0a25-4f72-be36-a78424d25e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045794494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.4045794494
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.377407678
Short name T132
Test name
Test status
Simulation time 54006323 ps
CPU time 1.05 seconds
Started Aug 06 04:34:00 PM PDT 24
Finished Aug 06 04:34:01 PM PDT 24
Peak memory 196076 kb
Host smart-7e1e0e06-1e73-4b78-bf46-f58d7dc95e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377407678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.377407678
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2030264979
Short name T459
Test name
Test status
Simulation time 296162899 ps
CPU time 1.35 seconds
Started Aug 06 04:33:49 PM PDT 24
Finished Aug 06 04:33:50 PM PDT 24
Peak memory 196812 kb
Host smart-8c390819-f336-4a3f-abc5-766656788129
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030264979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2030264979
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1897806560
Short name T670
Test name
Test status
Simulation time 4651170286 ps
CPU time 107.68 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:35:30 PM PDT 24
Peak memory 198552 kb
Host smart-0be78b12-cdd6-4f45-a1e3-7cd46661b635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897806560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1897806560
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.780515796
Short name T161
Test name
Test status
Simulation time 14353996 ps
CPU time 0.57 seconds
Started Aug 06 04:33:57 PM PDT 24
Finished Aug 06 04:33:58 PM PDT 24
Peak memory 194300 kb
Host smart-66981cda-73c5-4aad-9208-e90b233896ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780515796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.780515796
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3528652196
Short name T187
Test name
Test status
Simulation time 97218169 ps
CPU time 0.87 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 196920 kb
Host smart-7b2a931c-1616-43d7-a44e-b02bf61a7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528652196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3528652196
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.295533264
Short name T685
Test name
Test status
Simulation time 3560776196 ps
CPU time 20.47 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:34:04 PM PDT 24
Peak memory 197064 kb
Host smart-54f4854e-32c2-437d-b0c5-e17725cc2fc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295533264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.295533264
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1099265743
Short name T577
Test name
Test status
Simulation time 43819131 ps
CPU time 0.76 seconds
Started Aug 06 04:33:41 PM PDT 24
Finished Aug 06 04:33:42 PM PDT 24
Peak memory 196304 kb
Host smart-69c8e499-bdbd-4f79-ad1a-8d795123c696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099265743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1099265743
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1775666339
Short name T199
Test name
Test status
Simulation time 167805071 ps
CPU time 1.05 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:33:45 PM PDT 24
Peak memory 196184 kb
Host smart-5bc629b2-31b4-434b-93df-2ffe446e2fa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775666339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1775666339
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.746403318
Short name T163
Test name
Test status
Simulation time 349436791 ps
CPU time 3.38 seconds
Started Aug 06 04:33:52 PM PDT 24
Finished Aug 06 04:33:55 PM PDT 24
Peak memory 198516 kb
Host smart-9ff8d70b-c894-46e7-8f68-1bbc07244044
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746403318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.746403318
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1371303665
Short name T242
Test name
Test status
Simulation time 512415766 ps
CPU time 1.14 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 196080 kb
Host smart-c90d8661-122d-4769-b5c1-13643681182c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371303665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1371303665
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1453000396
Short name T338
Test name
Test status
Simulation time 142996780 ps
CPU time 0.88 seconds
Started Aug 06 04:33:55 PM PDT 24
Finished Aug 06 04:33:56 PM PDT 24
Peak memory 197060 kb
Host smart-b303a02d-9800-44ae-87ee-0ae54a6deffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453000396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1453000396
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.546949484
Short name T304
Test name
Test status
Simulation time 90859870 ps
CPU time 0.89 seconds
Started Aug 06 04:33:42 PM PDT 24
Finished Aug 06 04:33:43 PM PDT 24
Peak memory 197208 kb
Host smart-b0f44975-d628-4d0d-8247-36bfc160e2c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546949484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.546949484
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.143397801
Short name T545
Test name
Test status
Simulation time 605355693 ps
CPU time 5.01 seconds
Started Aug 06 04:33:44 PM PDT 24
Finished Aug 06 04:33:49 PM PDT 24
Peak memory 198324 kb
Host smart-25c34617-1a7a-42dd-93ef-7fae69da07f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143397801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.143397801
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2691959346
Short name T275
Test name
Test status
Simulation time 69114593 ps
CPU time 1.23 seconds
Started Aug 06 04:33:43 PM PDT 24
Finished Aug 06 04:33:45 PM PDT 24
Peak memory 197192 kb
Host smart-6a2d06d7-e0b0-47a0-aeaf-7c9e5dcc326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691959346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2691959346
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.649351247
Short name T13
Test name
Test status
Simulation time 213848962 ps
CPU time 1.08 seconds
Started Aug 06 04:33:52 PM PDT 24
Finished Aug 06 04:33:53 PM PDT 24
Peak memory 196268 kb
Host smart-87835eef-d968-48d3-991c-146cb1e7d4e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649351247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.649351247
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4139720931
Short name T6
Test name
Test status
Simulation time 13955312895 ps
CPU time 149.23 seconds
Started Aug 06 04:33:56 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 198652 kb
Host smart-1c06f629-3b04-4073-87d7-cc170eed3950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139720931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4139720931
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2105744241
Short name T583
Test name
Test status
Simulation time 20117237 ps
CPU time 0.62 seconds
Started Aug 06 04:34:01 PM PDT 24
Finished Aug 06 04:34:02 PM PDT 24
Peak memory 195036 kb
Host smart-44fd41af-d424-4fbf-884c-10b57cbabb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105744241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2105744241
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.678508900
Short name T605
Test name
Test status
Simulation time 92251687 ps
CPU time 0.83 seconds
Started Aug 06 04:33:46 PM PDT 24
Finished Aug 06 04:33:47 PM PDT 24
Peak memory 196776 kb
Host smart-c6eb357b-c9fe-4483-a8d1-ad021f2cfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678508900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.678508900
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3278161814
Short name T366
Test name
Test status
Simulation time 1094837791 ps
CPU time 7.56 seconds
Started Aug 06 04:34:01 PM PDT 24
Finished Aug 06 04:34:09 PM PDT 24
Peak memory 197308 kb
Host smart-ef0973a8-507e-4752-8810-29c75186dd2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278161814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3278161814
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2187886500
Short name T196
Test name
Test status
Simulation time 277882649 ps
CPU time 0.96 seconds
Started Aug 06 04:34:08 PM PDT 24
Finished Aug 06 04:34:09 PM PDT 24
Peak memory 197100 kb
Host smart-72272eaf-8dbc-4440-afe0-6c1d706b1582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187886500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2187886500
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.767965801
Short name T66
Test name
Test status
Simulation time 174599550 ps
CPU time 0.88 seconds
Started Aug 06 04:33:44 PM PDT 24
Finished Aug 06 04:33:45 PM PDT 24
Peak memory 196900 kb
Host smart-63ca8b18-8ce9-45aa-8219-a13ddb05ba9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767965801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.767965801
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3120595975
Short name T255
Test name
Test status
Simulation time 72819383 ps
CPU time 2.78 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 198468 kb
Host smart-d6e1a44f-b4a1-40f8-b96b-629663b70728
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120595975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3120595975
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.83638075
Short name T344
Test name
Test status
Simulation time 440645595 ps
CPU time 3.27 seconds
Started Aug 06 04:33:53 PM PDT 24
Finished Aug 06 04:33:56 PM PDT 24
Peak memory 197680 kb
Host smart-f9901702-6e55-40a6-8e0c-29c7136b4fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83638075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.83638075
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1658246796
Short name T639
Test name
Test status
Simulation time 49092374 ps
CPU time 0.86 seconds
Started Aug 06 04:33:50 PM PDT 24
Finished Aug 06 04:33:51 PM PDT 24
Peak memory 196344 kb
Host smart-6ae3e12d-aa72-463c-aea3-c89f54a1210a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658246796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1658246796
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3975463713
Short name T369
Test name
Test status
Simulation time 139292935 ps
CPU time 1.01 seconds
Started Aug 06 04:34:01 PM PDT 24
Finished Aug 06 04:34:02 PM PDT 24
Peak memory 196320 kb
Host smart-10af3558-0230-4faa-9d1c-2bf9006b3f4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975463713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3975463713
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2211031707
Short name T19
Test name
Test status
Simulation time 334083804 ps
CPU time 2.1 seconds
Started Aug 06 04:34:08 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 198488 kb
Host smart-cd9b402f-3f92-4e24-b0fb-a43ea21306d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211031707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2211031707
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.783560589
Short name T384
Test name
Test status
Simulation time 118895606 ps
CPU time 0.93 seconds
Started Aug 06 04:33:59 PM PDT 24
Finished Aug 06 04:34:00 PM PDT 24
Peak memory 197492 kb
Host smart-f5e16e4d-aa9d-448e-aaa2-50404b332e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783560589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.783560589
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1679942013
Short name T710
Test name
Test status
Simulation time 83827062 ps
CPU time 1.33 seconds
Started Aug 06 04:33:48 PM PDT 24
Finished Aug 06 04:33:50 PM PDT 24
Peak memory 198388 kb
Host smart-52b0cb57-0ee1-4160-811e-21f46296b57b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679942013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1679942013
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3790117018
Short name T335
Test name
Test status
Simulation time 35639148383 ps
CPU time 72.39 seconds
Started Aug 06 04:34:01 PM PDT 24
Finished Aug 06 04:35:14 PM PDT 24
Peak memory 198540 kb
Host smart-2a386847-881d-4eb4-8e74-37253011204e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790117018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3790117018
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2602237755
Short name T677
Test name
Test status
Simulation time 13565969 ps
CPU time 0.58 seconds
Started Aug 06 04:34:10 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 194300 kb
Host smart-2c218ce9-c2b4-400c-b94d-95296d39f127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602237755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2602237755
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1847273126
Short name T538
Test name
Test status
Simulation time 90069408 ps
CPU time 0.87 seconds
Started Aug 06 04:34:02 PM PDT 24
Finished Aug 06 04:34:03 PM PDT 24
Peak memory 196244 kb
Host smart-803632b2-45b0-4029-9c51-4fd469c3637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847273126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1847273126
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.451627618
Short name T328
Test name
Test status
Simulation time 615350222 ps
CPU time 8.82 seconds
Started Aug 06 04:34:03 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 198772 kb
Host smart-6535dfa1-c4fa-4f6b-9407-b342608f8639
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451627618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.451627618
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2881403929
Short name T51
Test name
Test status
Simulation time 81198388 ps
CPU time 0.98 seconds
Started Aug 06 04:34:15 PM PDT 24
Finished Aug 06 04:34:16 PM PDT 24
Peak memory 196892 kb
Host smart-2ef6c464-e21f-4e06-8b1a-aef34921193e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881403929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2881403929
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4276156550
Short name T151
Test name
Test status
Simulation time 52294092 ps
CPU time 1.37 seconds
Started Aug 06 04:34:02 PM PDT 24
Finished Aug 06 04:34:03 PM PDT 24
Peak memory 197368 kb
Host smart-a887b387-887f-46eb-9013-ffff0e171671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276156550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4276156550
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1091496755
Short name T356
Test name
Test status
Simulation time 84731906 ps
CPU time 3.7 seconds
Started Aug 06 04:34:08 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 198664 kb
Host smart-d86301f0-626f-4bfe-a411-b1cefeace141
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091496755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1091496755
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2873929539
Short name T626
Test name
Test status
Simulation time 418107246 ps
CPU time 2.17 seconds
Started Aug 06 04:34:16 PM PDT 24
Finished Aug 06 04:34:18 PM PDT 24
Peak memory 197612 kb
Host smart-e01da766-d51b-413a-b7bc-1ecc09ddfdbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873929539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2873929539
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2691279294
Short name T549
Test name
Test status
Simulation time 28556185 ps
CPU time 0.87 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:13 PM PDT 24
Peak memory 197744 kb
Host smart-ff95e71e-5bcb-47d7-a49c-6f739245879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691279294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2691279294
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3136757902
Short name T270
Test name
Test status
Simulation time 85839220 ps
CPU time 0.88 seconds
Started Aug 06 04:34:16 PM PDT 24
Finished Aug 06 04:34:17 PM PDT 24
Peak memory 196300 kb
Host smart-294a9b1e-009a-4b95-a9c1-4528729b376a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136757902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3136757902
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.487225909
Short name T513
Test name
Test status
Simulation time 188769021 ps
CPU time 2.24 seconds
Started Aug 06 04:34:02 PM PDT 24
Finished Aug 06 04:34:04 PM PDT 24
Peak memory 198408 kb
Host smart-8dd6681c-5085-4478-98ec-c2d697dbc717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487225909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.487225909
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1772944291
Short name T144
Test name
Test status
Simulation time 223731615 ps
CPU time 1.19 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 196268 kb
Host smart-e9e4bee3-45f9-4316-be32-11e5ed3541f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772944291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1772944291
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2021248546
Short name T499
Test name
Test status
Simulation time 429999824 ps
CPU time 1.24 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:12 PM PDT 24
Peak memory 196956 kb
Host smart-ad8b7313-aac1-4e56-9beb-9de2422867a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021248546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2021248546
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2506572520
Short name T565
Test name
Test status
Simulation time 23942338765 ps
CPU time 142.94 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:36:36 PM PDT 24
Peak memory 198576 kb
Host smart-8222265c-439e-4b9b-9a01-daa7d154b2d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506572520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2506572520
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.103042835
Short name T623
Test name
Test status
Simulation time 45280475451 ps
CPU time 543.41 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:43:09 PM PDT 24
Peak memory 198680 kb
Host smart-6c9b9caf-af09-448c-b078-bffcfe83c0de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=103042835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.103042835
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3457198341
Short name T690
Test name
Test status
Simulation time 35384538 ps
CPU time 0.59 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 194468 kb
Host smart-80c73ed8-ccf1-45c8-868c-0eeb993a431c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457198341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3457198341
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1736660458
Short name T133
Test name
Test status
Simulation time 76323564 ps
CPU time 0.93 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 196844 kb
Host smart-c4ed0f04-ad1b-4a97-8cd8-808d34958f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736660458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1736660458
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1219826331
Short name T65
Test name
Test status
Simulation time 882844601 ps
CPU time 23.96 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:36 PM PDT 24
Peak memory 195840 kb
Host smart-40382d62-4c5c-4145-9650-80564777ce90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219826331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1219826331
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3099848588
Short name T465
Test name
Test status
Simulation time 245277693 ps
CPU time 0.94 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:06 PM PDT 24
Peak memory 196428 kb
Host smart-5db86e8a-da20-407d-a6ea-145e1f510a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099848588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3099848588
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2639774001
Short name T331
Test name
Test status
Simulation time 95442053 ps
CPU time 1.34 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 198468 kb
Host smart-706b8a24-2b61-47ea-b70e-bf4abbbfa21e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639774001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2639774001
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1006823435
Short name T236
Test name
Test status
Simulation time 314791140 ps
CPU time 3.25 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:34:16 PM PDT 24
Peak memory 198568 kb
Host smart-e3735c06-b328-4700-9df6-ad6d15c1bdaa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006823435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1006823435
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2564710029
Short name T215
Test name
Test status
Simulation time 25217726 ps
CPU time 1.01 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 195872 kb
Host smart-85da89a2-9091-4571-bcd5-f6fe1741d28c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564710029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2564710029
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2050373261
Short name T180
Test name
Test status
Simulation time 73069455 ps
CPU time 0.84 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 197008 kb
Host smart-a1463b3e-bd8c-4c1b-a51e-cc084b349b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050373261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2050373261
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3065859474
Short name T440
Test name
Test status
Simulation time 378421932 ps
CPU time 0.86 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 196960 kb
Host smart-9c064c45-ce3f-4996-b0c7-3763032a5a8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065859474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3065859474
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1953104839
Short name T50
Test name
Test status
Simulation time 294058525 ps
CPU time 2.05 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 198404 kb
Host smart-5517cadb-7ce1-4e53-89f4-4beb0e21b51d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953104839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1953104839
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1823279953
Short name T489
Test name
Test status
Simulation time 181474205 ps
CPU time 1.29 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:06 PM PDT 24
Peak memory 197120 kb
Host smart-8b8a866c-676d-408f-9b47-3eee696036aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823279953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1823279953
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3852395419
Short name T643
Test name
Test status
Simulation time 195689311 ps
CPU time 1.01 seconds
Started Aug 06 04:34:02 PM PDT 24
Finished Aug 06 04:34:03 PM PDT 24
Peak memory 196176 kb
Host smart-417a8466-8251-478a-883d-73f7def004cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852395419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3852395419
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3121502431
Short name T533
Test name
Test status
Simulation time 17007401550 ps
CPU time 61.47 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:35:13 PM PDT 24
Peak memory 198588 kb
Host smart-d044f6b5-eb51-49cd-bc25-de6bf7e9498d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121502431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3121502431
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.729921895
Short name T76
Test name
Test status
Simulation time 174013489631 ps
CPU time 827.43 seconds
Started Aug 06 04:34:03 PM PDT 24
Finished Aug 06 04:47:51 PM PDT 24
Peak memory 198628 kb
Host smart-5e7212bf-db57-47dc-bbd4-0e60099431e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=729921895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.729921895
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.340974212
Short name T629
Test name
Test status
Simulation time 66912998 ps
CPU time 0.57 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 194528 kb
Host smart-7c033145-e455-40a4-b219-ca1c198297d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340974212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.340974212
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3877854915
Short name T534
Test name
Test status
Simulation time 201362819 ps
CPU time 0.9 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 196148 kb
Host smart-dd4498cd-9966-4327-815c-0392c62997cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877854915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3877854915
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2711926802
Short name T240
Test name
Test status
Simulation time 2706718016 ps
CPU time 18.29 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:30 PM PDT 24
Peak memory 197376 kb
Host smart-6ae31b03-48e4-47dc-a83c-be434afcff17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711926802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2711926802
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2522926278
Short name T640
Test name
Test status
Simulation time 34220474 ps
CPU time 0.69 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:13 PM PDT 24
Peak memory 194916 kb
Host smart-295246cf-d572-41a6-8d03-c7c32356571e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522926278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2522926278
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1994518032
Short name T248
Test name
Test status
Simulation time 68714454 ps
CPU time 0.72 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 195796 kb
Host smart-0877165e-ef40-4a15-a6eb-4751b8e532c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994518032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1994518032
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4032303652
Short name T290
Test name
Test status
Simulation time 125025512 ps
CPU time 2.53 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:14 PM PDT 24
Peak memory 198560 kb
Host smart-4b2b5650-8374-41a8-9580-8b73cfd341d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032303652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4032303652
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.247513574
Short name T687
Test name
Test status
Simulation time 915888320 ps
CPU time 2.98 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:14 PM PDT 24
Peak memory 197756 kb
Host smart-b0785973-2736-4b8f-9c8c-e9ff89786c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247513574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
247513574
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2068088152
Short name T208
Test name
Test status
Simulation time 45020684 ps
CPU time 0.9 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 196480 kb
Host smart-6910a5b7-8dbe-46f9-852c-7fb221f69e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068088152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2068088152
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2837375998
Short name T491
Test name
Test status
Simulation time 73726462 ps
CPU time 0.82 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 195768 kb
Host smart-967c3142-1ece-45bc-87db-0e40f39e12a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837375998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2837375998
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1799412892
Short name T289
Test name
Test status
Simulation time 106293895 ps
CPU time 4.13 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 198404 kb
Host smart-a415d850-face-4e19-be8c-6320f81bf0bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799412892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1799412892
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1931268168
Short name T392
Test name
Test status
Simulation time 74846861 ps
CPU time 1.13 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 196900 kb
Host smart-f2e78a03-6978-42de-a72e-c73829e1791a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931268168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1931268168
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3435481308
Short name T607
Test name
Test status
Simulation time 676705162 ps
CPU time 1.16 seconds
Started Aug 06 04:34:03 PM PDT 24
Finished Aug 06 04:34:04 PM PDT 24
Peak memory 196884 kb
Host smart-2ef7a1fb-4caa-4065-95af-37b9c6c6e584
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435481308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3435481308
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3984259790
Short name T638
Test name
Test status
Simulation time 92484633392 ps
CPU time 202.47 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:37:34 PM PDT 24
Peak memory 198536 kb
Host smart-b5c6260d-b55f-46a5-a225-be4e35174ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984259790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3984259790
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3749755753
Short name T409
Test name
Test status
Simulation time 86960720193 ps
CPU time 1681.39 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 05:02:14 PM PDT 24
Peak memory 198656 kb
Host smart-4592c2d2-ca8c-481b-a845-bc068eebf618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3749755753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3749755753
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1896955315
Short name T398
Test name
Test status
Simulation time 43690834 ps
CPU time 0.59 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 194248 kb
Host smart-504b38d9-c78a-4c2d-962c-d9acae592433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896955315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1896955315
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2953977799
Short name T334
Test name
Test status
Simulation time 45354752 ps
CPU time 0.69 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 195260 kb
Host smart-f42b4c2c-8860-4fb3-9d79-552d31d77bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953977799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2953977799
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1214050011
Short name T363
Test name
Test status
Simulation time 205309434 ps
CPU time 6.58 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:16 PM PDT 24
Peak memory 196024 kb
Host smart-db9d2708-d402-4e5f-9a71-acae7c8614f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214050011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1214050011
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1922766120
Short name T641
Test name
Test status
Simulation time 1162554368 ps
CPU time 1.03 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 196724 kb
Host smart-2916661b-476f-4d3f-8c37-4e6d7508ef22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922766120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1922766120
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1226498697
Short name T273
Test name
Test status
Simulation time 86020296 ps
CPU time 0.95 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 196572 kb
Host smart-dddd2b79-9691-4fcc-b7be-44ae7a110ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226498697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1226498697
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.51373977
Short name T283
Test name
Test status
Simulation time 27052906 ps
CPU time 1.18 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 198012 kb
Host smart-591c09dd-1d1c-47f7-8020-8096ec8482dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51373977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.gpio_intr_with_filter_rand_intr_event.51373977
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3385364503
Short name T664
Test name
Test status
Simulation time 1696637652 ps
CPU time 2.06 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:09 PM PDT 24
Peak memory 197660 kb
Host smart-f56363c1-746c-4dde-99df-00619256b838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385364503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3385364503
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2315273372
Short name T520
Test name
Test status
Simulation time 56488936 ps
CPU time 1.17 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 198500 kb
Host smart-0e44c52f-11d0-451c-bd12-ad6333e3d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315273372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2315273372
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.800179141
Short name T194
Test name
Test status
Simulation time 251405661 ps
CPU time 1.26 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 198528 kb
Host smart-f7b97da5-59c9-4ce8-8099-b3b3e3f1aa07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800179141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.800179141
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3602586022
Short name T627
Test name
Test status
Simulation time 1024966382 ps
CPU time 4.43 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:12 PM PDT 24
Peak memory 198288 kb
Host smart-5017b726-4560-43b5-a238-e004df3ce1ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602586022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3602586022
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.57762992
Short name T594
Test name
Test status
Simulation time 559311132 ps
CPU time 1.12 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:34:14 PM PDT 24
Peak memory 196756 kb
Host smart-eeb7c40c-7244-4d92-a773-5363e6bfead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57762992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.57762992
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1886788041
Short name T70
Test name
Test status
Simulation time 86059859 ps
CPU time 1.33 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 196260 kb
Host smart-8422edc1-36d5-426d-9752-f3dddaa687fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886788041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1886788041
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.712411842
Short name T309
Test name
Test status
Simulation time 36975706847 ps
CPU time 124.14 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:36:17 PM PDT 24
Peak memory 198680 kb
Host smart-a32151db-111d-4683-800b-faa7b6c4f184
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712411842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.712411842
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2438709465
Short name T52
Test name
Test status
Simulation time 45079785089 ps
CPU time 1210.8 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:54:16 PM PDT 24
Peak memory 198736 kb
Host smart-14041036-e035-45db-8af1-63156b717e37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2438709465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2438709465
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.273529897
Short name T569
Test name
Test status
Simulation time 25709308 ps
CPU time 0.57 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:12 PM PDT 24
Peak memory 195972 kb
Host smart-970cd434-a804-4589-8d9c-cd08a8da379c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273529897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.273529897
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.184590554
Short name T355
Test name
Test status
Simulation time 129129807 ps
CPU time 0.8 seconds
Started Aug 06 04:34:14 PM PDT 24
Finished Aug 06 04:34:15 PM PDT 24
Peak memory 196592 kb
Host smart-bdeeb602-087e-4e87-a1a4-e38e8447f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184590554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.184590554
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2712506240
Short name T428
Test name
Test status
Simulation time 258799188 ps
CPU time 13.42 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 197332 kb
Host smart-dfd037c2-ca18-4ce1-b707-919087c91c75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712506240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2712506240
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2740116861
Short name T653
Test name
Test status
Simulation time 342304123 ps
CPU time 0.77 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:12 PM PDT 24
Peak memory 196384 kb
Host smart-56735111-3e8f-4956-87bd-5a695f432a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740116861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2740116861
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2622776787
Short name T181
Test name
Test status
Simulation time 82416777 ps
CPU time 0.78 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 195920 kb
Host smart-0fa56e11-b4d3-41ab-8c8e-76048415fae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622776787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2622776787
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1613280834
Short name T672
Test name
Test status
Simulation time 247454926 ps
CPU time 1.27 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 198460 kb
Host smart-5b8fe30d-78bb-4d53-bf08-ee8b0a185f53
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613280834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1613280834
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2513139605
Short name T253
Test name
Test status
Simulation time 222048518 ps
CPU time 2.64 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 197608 kb
Host smart-731ac296-aa34-458d-91fa-3a6303f6a83b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513139605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2513139605
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3317512845
Short name T652
Test name
Test status
Simulation time 81936828 ps
CPU time 1.06 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:34:14 PM PDT 24
Peak memory 197104 kb
Host smart-ae7f67bd-0aa3-48ce-92d6-9420f218502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317512845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3317512845
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4241596376
Short name T268
Test name
Test status
Simulation time 374811500 ps
CPU time 1.07 seconds
Started Aug 06 04:34:07 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 196880 kb
Host smart-7f26a20f-51a0-4b13-b10e-c145cef0eab0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241596376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4241596376
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.82045779
Short name T18
Test name
Test status
Simulation time 847841115 ps
CPU time 4.16 seconds
Started Aug 06 04:34:11 PM PDT 24
Finished Aug 06 04:34:16 PM PDT 24
Peak memory 198404 kb
Host smart-301d097e-92a7-453f-afab-4533b1f89111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82045779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand
om_long_reg_writes_reg_reads.82045779
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2125772731
Short name T471
Test name
Test status
Simulation time 82085869 ps
CPU time 1.43 seconds
Started Aug 06 04:34:12 PM PDT 24
Finished Aug 06 04:34:14 PM PDT 24
Peak memory 198436 kb
Host smart-097a74f6-7ad5-4d85-be0c-a9457483935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125772731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2125772731
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2065191107
Short name T631
Test name
Test status
Simulation time 130378895 ps
CPU time 1.13 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:06 PM PDT 24
Peak memory 196988 kb
Host smart-135835a0-ee37-4e8a-975c-ef64790c15f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065191107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2065191107
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.563452910
Short name T532
Test name
Test status
Simulation time 4773955198 ps
CPU time 29.65 seconds
Started Aug 06 04:34:09 PM PDT 24
Finished Aug 06 04:34:38 PM PDT 24
Peak memory 198620 kb
Host smart-74662d59-62c0-4249-8cd4-1f99b28b1849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563452910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.563452910
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3267228583
Short name T299
Test name
Test status
Simulation time 16421426 ps
CPU time 0.66 seconds
Started Aug 06 04:34:10 PM PDT 24
Finished Aug 06 04:34:10 PM PDT 24
Peak memory 195352 kb
Host smart-575c1b88-c5fb-4336-ac34-f2c213531885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267228583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3267228583
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2060284699
Short name T387
Test name
Test status
Simulation time 173703468 ps
CPU time 0.67 seconds
Started Aug 06 04:34:10 PM PDT 24
Finished Aug 06 04:34:11 PM PDT 24
Peak memory 195124 kb
Host smart-5e344e92-dbff-46aa-a73c-f84243d30879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060284699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2060284699
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1846707874
Short name T101
Test name
Test status
Simulation time 1044246090 ps
CPU time 7.94 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:13 PM PDT 24
Peak memory 196528 kb
Host smart-208a5829-9d32-4522-876f-9f5712baf97c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846707874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1846707874
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3628959748
Short name T425
Test name
Test status
Simulation time 366823889 ps
CPU time 1.04 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 198304 kb
Host smart-b5ac9fb9-9662-4c9f-b7d1-5b38007e1be6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628959748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3628959748
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3055778435
Short name T595
Test name
Test status
Simulation time 90658710 ps
CPU time 0.73 seconds
Started Aug 06 04:34:02 PM PDT 24
Finished Aug 06 04:34:03 PM PDT 24
Peak memory 194696 kb
Host smart-4002578a-98ef-443b-895e-b59d75b6b257
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055778435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3055778435
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2334115038
Short name T221
Test name
Test status
Simulation time 74006731 ps
CPU time 2.84 seconds
Started Aug 06 04:34:13 PM PDT 24
Finished Aug 06 04:34:16 PM PDT 24
Peak memory 196828 kb
Host smart-ad03d359-f208-410e-a08c-8f57c64bbcba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334115038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2334115038
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.294228742
Short name T389
Test name
Test status
Simulation time 307651292 ps
CPU time 1.71 seconds
Started Aug 06 04:34:00 PM PDT 24
Finished Aug 06 04:34:02 PM PDT 24
Peak memory 196496 kb
Host smart-220d50a8-605b-40c8-ac6b-798d224d5bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294228742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
294228742
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.172911244
Short name T195
Test name
Test status
Simulation time 30939207 ps
CPU time 0.78 seconds
Started Aug 06 04:34:04 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 195616 kb
Host smart-e37f1fbf-c6eb-4c68-b44f-d904157c8da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172911244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.172911244
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1860375898
Short name T120
Test name
Test status
Simulation time 117637438 ps
CPU time 1.15 seconds
Started Aug 06 04:34:03 PM PDT 24
Finished Aug 06 04:34:05 PM PDT 24
Peak memory 196532 kb
Host smart-85ff6b92-54d6-4008-a564-f7407319b8e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860375898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1860375898
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3919398523
Short name T649
Test name
Test status
Simulation time 207007959 ps
CPU time 2.54 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:09 PM PDT 24
Peak memory 198408 kb
Host smart-667b2c85-f991-4f8d-9a03-141339f999d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919398523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3919398523
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1052455731
Short name T337
Test name
Test status
Simulation time 294843580 ps
CPU time 1.36 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:08 PM PDT 24
Peak memory 197236 kb
Host smart-f7b93b19-4f32-435a-b3af-4468371ed493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052455731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1052455731
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3954978382
Short name T711
Test name
Test status
Simulation time 674361110 ps
CPU time 1.46 seconds
Started Aug 06 04:34:05 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 198324 kb
Host smart-48696727-f7f0-45da-bbba-968359806a77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954978382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3954978382
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1751054026
Short name T378
Test name
Test status
Simulation time 86979559494 ps
CPU time 183.76 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:37:10 PM PDT 24
Peak memory 198568 kb
Host smart-b2536d09-b8ca-4bcc-84cf-01713b9b6a55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751054026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1751054026
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2326325792
Short name T385
Test name
Test status
Simulation time 26095994 ps
CPU time 0.56 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 194340 kb
Host smart-dffd8a1c-a86d-4f24-a3e2-6d2469fa74ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326325792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2326325792
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2265308361
Short name T108
Test name
Test status
Simulation time 55499645 ps
CPU time 0.9 seconds
Started Aug 06 04:34:17 PM PDT 24
Finished Aug 06 04:34:18 PM PDT 24
Peak memory 196220 kb
Host smart-41de9122-9e9b-4afd-b09a-bf446cfae90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265308361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2265308361
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.546806061
Short name T399
Test name
Test status
Simulation time 671307634 ps
CPU time 23.38 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 197424 kb
Host smart-4479b0ba-9ef1-467d-8912-7ed5d41542c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546806061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.546806061
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2753696123
Short name T403
Test name
Test status
Simulation time 412918240 ps
CPU time 0.9 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 196432 kb
Host smart-07100009-0cb3-4195-8897-662820317782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753696123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2753696123
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3657651803
Short name T213
Test name
Test status
Simulation time 39322973 ps
CPU time 0.8 seconds
Started Aug 06 04:34:18 PM PDT 24
Finished Aug 06 04:34:19 PM PDT 24
Peak memory 196688 kb
Host smart-90d34313-2c3e-40d0-9003-7704292bc4db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657651803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3657651803
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.950790862
Short name T541
Test name
Test status
Simulation time 91587836 ps
CPU time 3.42 seconds
Started Aug 06 04:34:27 PM PDT 24
Finished Aug 06 04:34:31 PM PDT 24
Peak memory 198400 kb
Host smart-53d192a6-d458-4dbe-8fd5-21ebc4fdd035
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950790862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.950790862
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2321889267
Short name T671
Test name
Test status
Simulation time 109735772 ps
CPU time 2.2 seconds
Started Aug 06 04:34:18 PM PDT 24
Finished Aug 06 04:34:21 PM PDT 24
Peak memory 197916 kb
Host smart-b56ae378-726a-420d-863a-35d5c58a2ce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321889267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2321889267
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3376987235
Short name T223
Test name
Test status
Simulation time 34304829 ps
CPU time 1.42 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 198488 kb
Host smart-09c170ce-82bf-4ea9-979a-39ddc3c2df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376987235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3376987235
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2069753187
Short name T633
Test name
Test status
Simulation time 54555869 ps
CPU time 1.05 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 197332 kb
Host smart-51f05a97-c2e6-41e2-af7a-eb392dabcc62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069753187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2069753187
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3475304552
Short name T336
Test name
Test status
Simulation time 417841913 ps
CPU time 2.06 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 198496 kb
Host smart-79f3c0e1-0b24-4885-809e-8ff5a76adc2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475304552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3475304552
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.658054547
Short name T203
Test name
Test status
Simulation time 259352826 ps
CPU time 1.1 seconds
Started Aug 06 04:34:06 PM PDT 24
Finished Aug 06 04:34:07 PM PDT 24
Peak memory 196228 kb
Host smart-e8c420ee-fea9-41b6-8262-f16da20365cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658054547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.658054547
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1787287837
Short name T286
Test name
Test status
Simulation time 48993590 ps
CPU time 1.06 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 195852 kb
Host smart-43042e5a-8230-4561-aa20-eef1c9bc60df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787287837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1787287837
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3130729110
Short name T256
Test name
Test status
Simulation time 44717491062 ps
CPU time 130.19 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:36:31 PM PDT 24
Peak memory 198656 kb
Host smart-5080270f-4adc-409c-a256-51ff28f6aeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130729110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3130729110
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1276482342
Short name T143
Test name
Test status
Simulation time 15158059 ps
CPU time 0.58 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 194536 kb
Host smart-c5ff5882-9e68-46a4-a41d-b214d2de9df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276482342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1276482342
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.896077473
Short name T449
Test name
Test status
Simulation time 14282188 ps
CPU time 0.62 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:11 PM PDT 24
Peak memory 194304 kb
Host smart-715565fa-179a-47f6-b860-2a556f2d815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896077473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.896077473
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3059508500
Short name T44
Test name
Test status
Simulation time 1779902430 ps
CPU time 11.23 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 197796 kb
Host smart-d658e7d0-f84b-498e-a8b1-affe1f4d9bd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059508500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3059508500
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.905783229
Short name T365
Test name
Test status
Simulation time 88708231 ps
CPU time 0.59 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 195388 kb
Host smart-011326db-f8d0-4c71-b159-ea962155df16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905783229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.905783229
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3419902595
Short name T104
Test name
Test status
Simulation time 283920996 ps
CPU time 1.17 seconds
Started Aug 06 04:33:13 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 196480 kb
Host smart-9c65b7b0-75fb-49e8-9391-fb7fdb35c40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419902595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3419902595
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2360331636
Short name T578
Test name
Test status
Simulation time 78303550 ps
CPU time 3.3 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 198336 kb
Host smart-0094c979-abb5-460e-ba6e-09b35bd3f2c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360331636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2360331636
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.166563053
Short name T343
Test name
Test status
Simulation time 67678879 ps
CPU time 1.52 seconds
Started Aug 06 04:33:08 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 196212 kb
Host smart-f23350b8-d1ad-445d-b3f2-13e957c613e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166563053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.166563053
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2006127527
Short name T684
Test name
Test status
Simulation time 34092129 ps
CPU time 1.06 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 196324 kb
Host smart-3b2b35ec-e185-405e-bddd-5e5ddba92123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006127527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2006127527
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2687517442
Short name T139
Test name
Test status
Simulation time 18396486 ps
CPU time 0.66 seconds
Started Aug 06 04:33:13 PM PDT 24
Finished Aug 06 04:33:13 PM PDT 24
Peak memory 195420 kb
Host smart-25aa5020-8f75-41c6-8977-b1e3b82f87c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687517442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2687517442
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3433198572
Short name T7
Test name
Test status
Simulation time 260720310 ps
CPU time 1.3 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 197288 kb
Host smart-3a5b9206-88d5-4e2b-9d2d-43b8cfe7811b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433198572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3433198572
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.606683543
Short name T41
Test name
Test status
Simulation time 38565807 ps
CPU time 0.75 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 215160 kb
Host smart-e07b614d-dbbc-450b-874f-0435572aba9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606683543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.606683543
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.4260518780
Short name T563
Test name
Test status
Simulation time 275690584 ps
CPU time 1.03 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 196852 kb
Host smart-7d0a35b0-efd5-4efd-8905-45592611f1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260518780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4260518780
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1007589331
Short name T479
Test name
Test status
Simulation time 348298770 ps
CPU time 1.3 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 197156 kb
Host smart-7cdc3890-e9ff-4016-9d44-645db51aca8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007589331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1007589331
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.409525782
Short name T642
Test name
Test status
Simulation time 8490929187 ps
CPU time 97.36 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:35:01 PM PDT 24
Peak memory 198612 kb
Host smart-ac94084a-3507-4f12-8db2-e2fedeed4f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409525782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.409525782
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3175433459
Short name T417
Test name
Test status
Simulation time 190620492736 ps
CPU time 455.71 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:41:00 PM PDT 24
Peak memory 198660 kb
Host smart-069e71fe-69b6-48df-a204-5321abe7dce8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3175433459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3175433459
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.877942966
Short name T167
Test name
Test status
Simulation time 16736395 ps
CPU time 0.59 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 194236 kb
Host smart-2d4f1560-fe9a-415b-8819-b0d3b26e38aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877942966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.877942966
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3209838859
Short name T509
Test name
Test status
Simulation time 79809060 ps
CPU time 0.97 seconds
Started Aug 06 04:34:26 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 197220 kb
Host smart-f18aefe0-877f-4258-9cb5-f103e465fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209838859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3209838859
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1466361648
Short name T142
Test name
Test status
Simulation time 1083792036 ps
CPU time 26.51 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 195912 kb
Host smart-c8d68865-c29e-4422-8f2d-bf6bdde5f664
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466361648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1466361648
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.514793455
Short name T103
Test name
Test status
Simulation time 263247515 ps
CPU time 1.06 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 198264 kb
Host smart-91d2e11c-6993-4047-b224-5e830b21fcec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514793455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.514793455
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4193793287
Short name T164
Test name
Test status
Simulation time 175886209 ps
CPU time 1.22 seconds
Started Aug 06 04:34:17 PM PDT 24
Finished Aug 06 04:34:18 PM PDT 24
Peak memory 196236 kb
Host smart-268aca49-3116-4f70-9dc1-21cecf83bf6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193793287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4193793287
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3268914637
Short name T316
Test name
Test status
Simulation time 92188687 ps
CPU time 2.27 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 196944 kb
Host smart-baa73fe0-ab9f-40e8-85a8-54af244eae6d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268914637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3268914637
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2001756630
Short name T332
Test name
Test status
Simulation time 748331595 ps
CPU time 3.16 seconds
Started Aug 06 04:34:18 PM PDT 24
Finished Aug 06 04:34:21 PM PDT 24
Peak memory 197360 kb
Host smart-bfe8032c-bd1c-4649-a153-ad91422a6c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001756630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2001756630
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2069620647
Short name T517
Test name
Test status
Simulation time 20030595 ps
CPU time 0.75 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 195672 kb
Host smart-91ac4217-02a3-4986-af10-d5bd148eb693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069620647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2069620647
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.4236480046
Short name T342
Test name
Test status
Simulation time 91703982 ps
CPU time 0.79 seconds
Started Aug 06 04:34:16 PM PDT 24
Finished Aug 06 04:34:17 PM PDT 24
Peak memory 196540 kb
Host smart-006b3461-db84-4345-b373-d6c476d20e37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236480046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.4236480046
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4203824847
Short name T9
Test name
Test status
Simulation time 831730552 ps
CPU time 2.58 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 198336 kb
Host smart-077fd452-7249-420c-b84f-dfb8661f45a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203824847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4203824847
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3592368191
Short name T121
Test name
Test status
Simulation time 248920225 ps
CPU time 1.23 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 197556 kb
Host smart-e3f4057f-2feb-4d81-a87f-6ebbd3a230ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592368191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3592368191
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1609790166
Short name T191
Test name
Test status
Simulation time 132800019 ps
CPU time 1.33 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 197216 kb
Host smart-e10b5c6d-8745-42ea-b2a0-03f60c85bf1f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609790166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1609790166
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.328080625
Short name T567
Test name
Test status
Simulation time 14527892981 ps
CPU time 192.7 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:37:38 PM PDT 24
Peak memory 198508 kb
Host smart-d9ea6bf7-929b-4096-8d25-c3a0c6a4f546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328080625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.328080625
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4149771337
Short name T579
Test name
Test status
Simulation time 50409093 ps
CPU time 0.58 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:21 PM PDT 24
Peak memory 195388 kb
Host smart-1f8d4b98-bdb9-41b3-a381-543927c675d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149771337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4149771337
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2384655890
Short name T281
Test name
Test status
Simulation time 178073932 ps
CPU time 0.87 seconds
Started Aug 06 04:34:19 PM PDT 24
Finished Aug 06 04:34:20 PM PDT 24
Peak memory 196724 kb
Host smart-915c92ad-1768-4f32-bee4-53c5aa2b74d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384655890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2384655890
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2582048413
Short name T324
Test name
Test status
Simulation time 441274864 ps
CPU time 5.64 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 198352 kb
Host smart-130de7b9-ccc7-4e63-9995-2272c43ea4d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582048413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2582048413
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1308646272
Short name T443
Test name
Test status
Simulation time 173016384 ps
CPU time 1.46 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 198372 kb
Host smart-1da0afc0-7968-4cfe-9b3a-8004790dd598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308646272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1308646272
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2984503482
Short name T410
Test name
Test status
Simulation time 53669382 ps
CPU time 1.23 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 197072 kb
Host smart-df4d91bd-793b-4e00-8785-bac5ab1d309b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984503482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2984503482
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3638757883
Short name T185
Test name
Test status
Simulation time 151253425 ps
CPU time 2.47 seconds
Started Aug 06 04:34:18 PM PDT 24
Finished Aug 06 04:34:20 PM PDT 24
Peak memory 197424 kb
Host smart-4eb488fd-61e8-4456-91d1-8c42ee661802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638757883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3638757883
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3231385937
Short name T441
Test name
Test status
Simulation time 34829645 ps
CPU time 1.25 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 197436 kb
Host smart-285caf4b-595d-4392-832f-787cb0637163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231385937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3231385937
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1246943229
Short name T166
Test name
Test status
Simulation time 118403853 ps
CPU time 0.71 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 194720 kb
Host smart-cac2523f-b52b-4d4e-9cda-486252aac5a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246943229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1246943229
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4000566321
Short name T411
Test name
Test status
Simulation time 70669300 ps
CPU time 3.15 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 198344 kb
Host smart-31957d4e-1992-4226-8a12-141af56fb08b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000566321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4000566321
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1553131743
Short name T266
Test name
Test status
Simulation time 40084798 ps
CPU time 0.91 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 196736 kb
Host smart-3bb3c188-06c4-442e-8448-018e295ec20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553131743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1553131743
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4005254619
Short name T467
Test name
Test status
Simulation time 351644714 ps
CPU time 1.07 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 196228 kb
Host smart-8e93c45b-6aeb-4db7-b8bf-5dcdc0bb38aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005254619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4005254619
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.54582878
Short name T593
Test name
Test status
Simulation time 6084217879 ps
CPU time 146.12 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:36:49 PM PDT 24
Peak memory 198588 kb
Host smart-f06bfae5-d5e2-43bb-be01-aa761bb9e68c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54582878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gp
io_stress_all.54582878
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1932315750
Short name T514
Test name
Test status
Simulation time 490786528093 ps
CPU time 2247.65 seconds
Started Aug 06 04:34:27 PM PDT 24
Finished Aug 06 05:11:55 PM PDT 24
Peak memory 198724 kb
Host smart-b225ed96-268e-4e4a-aa0d-d8869d89160c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1932315750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1932315750
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3272951324
Short name T662
Test name
Test status
Simulation time 12683442 ps
CPU time 0.59 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:34:21 PM PDT 24
Peak memory 194336 kb
Host smart-e27aec38-d9dd-4fc1-be6b-cf0b191dd0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272951324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3272951324
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3169691128
Short name T282
Test name
Test status
Simulation time 52138723 ps
CPU time 0.73 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 194512 kb
Host smart-86bf8839-e9ec-4110-b7be-38e4e6130162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169691128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3169691128
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4214128098
Short name T432
Test name
Test status
Simulation time 8466934999 ps
CPU time 16.99 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:34:37 PM PDT 24
Peak memory 197464 kb
Host smart-f074bfc6-6d09-4545-9ffa-782f7139db11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214128098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4214128098
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2844451614
Short name T353
Test name
Test status
Simulation time 21114137 ps
CPU time 0.61 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 194548 kb
Host smart-7185246c-2dbf-4198-96b3-2047e4830a76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844451614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2844451614
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2750023103
Short name T62
Test name
Test status
Simulation time 41229852 ps
CPU time 0.93 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 196916 kb
Host smart-2ef50ed3-8c2d-443b-8813-ce9423f047fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750023103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2750023103
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1224679324
Short name T625
Test name
Test status
Simulation time 358044847 ps
CPU time 3.71 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 198660 kb
Host smart-5a116d89-06ad-4718-844a-9751964630d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224679324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1224679324
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3071898184
Short name T107
Test name
Test status
Simulation time 148419686 ps
CPU time 1.33 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 196912 kb
Host smart-a01cef89-b215-462f-bad0-2dde9c83949b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071898184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3071898184
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.575142192
Short name T305
Test name
Test status
Simulation time 84818194 ps
CPU time 0.78 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 196512 kb
Host smart-8082568b-3475-4dc2-8c4c-33842538cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575142192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.575142192
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1799775581
Short name T128
Test name
Test status
Simulation time 260986706 ps
CPU time 1.01 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 196044 kb
Host smart-4b4df5bd-35ed-49f1-a71c-54d1861b5fda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799775581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1799775581
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.362746807
Short name T5
Test name
Test status
Simulation time 715395441 ps
CPU time 2.29 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 197572 kb
Host smart-21b71556-c59c-451a-8d16-ee2ca35dd25f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362746807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.362746807
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2169007299
Short name T574
Test name
Test status
Simulation time 85730846 ps
CPU time 1.13 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 196316 kb
Host smart-3620f402-ee5f-4477-859c-21121802eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169007299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2169007299
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4288334770
Short name T450
Test name
Test status
Simulation time 39655699 ps
CPU time 1.2 seconds
Started Aug 06 04:34:17 PM PDT 24
Finished Aug 06 04:34:18 PM PDT 24
Peak memory 196300 kb
Host smart-e8940fbe-8149-4be7-a6d6-1dd3435540df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288334770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4288334770
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3529401209
Short name T680
Test name
Test status
Simulation time 68188934921 ps
CPU time 174.9 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:37:16 PM PDT 24
Peak memory 198628 kb
Host smart-0efc473d-7281-4c44-b29b-85ab9c9212bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529401209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3529401209
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2030056775
Short name T457
Test name
Test status
Simulation time 76637177 ps
CPU time 0.54 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 194292 kb
Host smart-fb0a1e3f-4d70-4504-8bda-fe4fdf7fdee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030056775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2030056775
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1584157011
Short name T386
Test name
Test status
Simulation time 33497731 ps
CPU time 0.78 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 195632 kb
Host smart-9c5fb1b4-b237-41e7-9c6d-25ff69bfc060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584157011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1584157011
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3601735916
Short name T435
Test name
Test status
Simulation time 236050926 ps
CPU time 6.62 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:30 PM PDT 24
Peak memory 195968 kb
Host smart-c1a78755-1ebf-4c4d-9e7d-849d3d3b943c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601735916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3601735916
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.190067260
Short name T466
Test name
Test status
Simulation time 94682917 ps
CPU time 1.03 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 197464 kb
Host smart-900047ea-4fc1-48f7-961e-84220382f31c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190067260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.190067260
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2733714090
Short name T310
Test name
Test status
Simulation time 22888813 ps
CPU time 0.64 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 194520 kb
Host smart-60846db7-f061-46a8-adac-ab835864c3d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733714090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2733714090
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1030381682
Short name T644
Test name
Test status
Simulation time 29043066 ps
CPU time 1.28 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 197116 kb
Host smart-f65de31a-6b2c-44df-ac2c-436ab49549bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030381682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1030381682
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3480470169
Short name T238
Test name
Test status
Simulation time 555567686 ps
CPU time 1.78 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 196540 kb
Host smart-43cd9524-bcd5-407b-8a79-a7ac4370e83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480470169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3480470169
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1755863487
Short name T612
Test name
Test status
Simulation time 13028609 ps
CPU time 0.63 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 194584 kb
Host smart-6ef92e4b-5cdc-4f05-8b25-ddfcf426f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755863487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1755863487
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2335522897
Short name T109
Test name
Test status
Simulation time 152367049 ps
CPU time 1.12 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 196420 kb
Host smart-4ddce03f-fd65-4152-90dc-ab65444f205a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335522897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2335522897
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.697332432
Short name T341
Test name
Test status
Simulation time 284673498 ps
CPU time 3.19 seconds
Started Aug 06 04:34:26 PM PDT 24
Finished Aug 06 04:34:29 PM PDT 24
Peak memory 198456 kb
Host smart-f74e618a-ed31-4adf-b634-e9b72e331f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697332432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.697332432
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4166833988
Short name T318
Test name
Test status
Simulation time 22578689 ps
CPU time 0.76 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 195612 kb
Host smart-98054f93-db33-4fb8-bc5c-8587cb87e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166833988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4166833988
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3731882182
Short name T265
Test name
Test status
Simulation time 48200620 ps
CPU time 1.28 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 198476 kb
Host smart-5c5d19c6-4bb8-46c2-9bf0-5dc6e080431b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731882182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3731882182
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.928316680
Short name T596
Test name
Test status
Simulation time 2599910281 ps
CPU time 32.6 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:57 PM PDT 24
Peak memory 198600 kb
Host smart-7a17e235-f64b-4c7a-965a-1b277ff66721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928316680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.928316680
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.206843917
Short name T33
Test name
Test status
Simulation time 16809718 ps
CPU time 0.6 seconds
Started Aug 06 04:34:27 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 195004 kb
Host smart-fc2c4224-cb59-41d4-b2f1-97a3db59b17b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206843917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.206843917
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3491695910
Short name T261
Test name
Test status
Simulation time 112828512 ps
CPU time 0.67 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 194284 kb
Host smart-a06276bb-dd9d-4bfc-b3dd-daed8b91f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491695910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3491695910
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3200494740
Short name T174
Test name
Test status
Simulation time 1576064431 ps
CPU time 21.41 seconds
Started Aug 06 04:34:27 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 195940 kb
Host smart-4061d8b3-0253-4971-bf2e-8c7c526216f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200494740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3200494740
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3599617007
Short name T659
Test name
Test status
Simulation time 40884840 ps
CPU time 0.72 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 195196 kb
Host smart-5250c5da-9fb9-4044-a7c9-c6356d1d40ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599617007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3599617007
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1648970713
Short name T153
Test name
Test status
Simulation time 178762955 ps
CPU time 1.34 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 198460 kb
Host smart-b0044d61-65ca-445a-8eb0-40c963891251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648970713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1648970713
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2591061015
Short name T636
Test name
Test status
Simulation time 224868964 ps
CPU time 1.39 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 198692 kb
Host smart-c251bb5d-b994-402b-82fe-95873013ba9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591061015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2591061015
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2042998703
Short name T59
Test name
Test status
Simulation time 333103759 ps
CPU time 2.62 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 197748 kb
Host smart-67f9a218-8aa9-4443-b7b7-6aff8b1add73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042998703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2042998703
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2971481101
Short name T244
Test name
Test status
Simulation time 197036575 ps
CPU time 1 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 196164 kb
Host smart-38dd5bac-cc8e-46fa-b1cd-4951dd67cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971481101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2971481101
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.839635266
Short name T561
Test name
Test status
Simulation time 36441985 ps
CPU time 1 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 196908 kb
Host smart-dbbefdb0-a113-485d-8c47-2c66a97a498e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839635266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.839635266
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2265575968
Short name T456
Test name
Test status
Simulation time 1251906585 ps
CPU time 4.01 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:30 PM PDT 24
Peak memory 198476 kb
Host smart-c3ca19a0-82ab-4c9c-ac8c-08c2c968a2bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265575968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2265575968
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3799706717
Short name T379
Test name
Test status
Simulation time 101678708 ps
CPU time 0.9 seconds
Started Aug 06 04:34:23 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 196800 kb
Host smart-ba58f1e4-5a97-4aec-8059-7f378ae26ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799706717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3799706717
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3760240545
Short name T666
Test name
Test status
Simulation time 61151419 ps
CPU time 1.11 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 197004 kb
Host smart-515c9fa9-7118-46c7-ba39-821f917fe329
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760240545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3760240545
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3236825758
Short name T575
Test name
Test status
Simulation time 9126321566 ps
CPU time 95.02 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:35:55 PM PDT 24
Peak memory 198652 kb
Host smart-77cabf20-47a3-4602-a7d4-937bc49ec122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236825758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3236825758
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2863938256
Short name T24
Test name
Test status
Simulation time 20577364255 ps
CPU time 631.02 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:44:57 PM PDT 24
Peak memory 198848 kb
Host smart-42c662d4-5d50-4fa1-8e6d-0eca92abd64f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2863938256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2863938256
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1371852106
Short name T699
Test name
Test status
Simulation time 12681184 ps
CPU time 0.56 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 194364 kb
Host smart-6ffacc32-ee4c-4ef6-a58d-0302cd95e76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371852106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1371852106
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3924708874
Short name T130
Test name
Test status
Simulation time 75159113 ps
CPU time 0.71 seconds
Started Aug 06 04:34:27 PM PDT 24
Finished Aug 06 04:34:28 PM PDT 24
Peak memory 194608 kb
Host smart-c35cc605-3940-433f-9712-937f1264b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924708874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3924708874
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.523362065
Short name T382
Test name
Test status
Simulation time 766470823 ps
CPU time 20.3 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 197112 kb
Host smart-6b43c30b-a608-4c1e-ad77-440b34b2b530
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523362065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.523362065
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2349848740
Short name T592
Test name
Test status
Simulation time 68501657 ps
CPU time 0.75 seconds
Started Aug 06 04:34:26 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 195100 kb
Host smart-535cccea-b15e-49af-8c55-adba755d1d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349848740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2349848740
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.351994279
Short name T214
Test name
Test status
Simulation time 40498960 ps
CPU time 0.77 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 196464 kb
Host smart-d82abe5c-d73d-458b-82c5-5c97c4f87d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351994279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.351994279
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.965165025
Short name T715
Test name
Test status
Simulation time 62417266 ps
CPU time 1.33 seconds
Started Aug 06 04:34:25 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 196744 kb
Host smart-bdb31849-5d46-4a9a-94c8-3e75bd72d6b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965165025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.965165025
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.21911851
Short name T581
Test name
Test status
Simulation time 163623378 ps
CPU time 3.09 seconds
Started Aug 06 04:34:19 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 198488 kb
Host smart-79c195c1-3206-46a1-93fc-a471304ff8c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21911851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.21911851
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.4007593429
Short name T48
Test name
Test status
Simulation time 54726765 ps
CPU time 1.17 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:25 PM PDT 24
Peak memory 198492 kb
Host smart-a88fbe55-c475-471d-b533-660998c9e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007593429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.4007593429
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2661348170
Short name T235
Test name
Test status
Simulation time 62776908 ps
CPU time 0.81 seconds
Started Aug 06 04:34:22 PM PDT 24
Finished Aug 06 04:34:23 PM PDT 24
Peak memory 195724 kb
Host smart-ef8df7d9-bd86-4d07-a528-b9a40fae7851
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661348170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2661348170
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4091089026
Short name T209
Test name
Test status
Simulation time 82068627 ps
CPU time 3.69 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:34:24 PM PDT 24
Peak memory 198420 kb
Host smart-99bcb2e9-4f0a-4d5d-8c45-b04ef764bbfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091089026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4091089026
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.596827342
Short name T458
Test name
Test status
Simulation time 130874496 ps
CPU time 1.6 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:34:26 PM PDT 24
Peak memory 195940 kb
Host smart-09d70d97-4fb3-4fbf-9c40-7d49af283eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596827342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.596827342
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1276601077
Short name T137
Test name
Test status
Simulation time 42138243 ps
CPU time 0.91 seconds
Started Aug 06 04:34:26 PM PDT 24
Finished Aug 06 04:34:27 PM PDT 24
Peak memory 196592 kb
Host smart-d7cf6a7f-b7f0-4ce9-8c88-eb3f33d3ff26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276601077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1276601077
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1901727102
Short name T372
Test name
Test status
Simulation time 35904273999 ps
CPU time 234.44 seconds
Started Aug 06 04:34:24 PM PDT 24
Finished Aug 06 04:38:19 PM PDT 24
Peak memory 198632 kb
Host smart-cda81133-1339-4537-b7f9-34273a91b1ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901727102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1901727102
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1799346558
Short name T557
Test name
Test status
Simulation time 312528973815 ps
CPU time 1840.85 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 05:05:02 PM PDT 24
Peak memory 198788 kb
Host smart-f3d0dee8-690c-4590-9453-3974e46b3289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1799346558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1799346558
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4005164962
Short name T250
Test name
Test status
Simulation time 38564101 ps
CPU time 0.55 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:39 PM PDT 24
Peak memory 194416 kb
Host smart-77d1c266-ea01-4ad7-a51e-1bfcdebd8fe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005164962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4005164962
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3873313744
Short name T405
Test name
Test status
Simulation time 177766832 ps
CPU time 0.73 seconds
Started Aug 06 04:34:46 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 195488 kb
Host smart-62471fb6-4eec-4c76-ade4-fbb8c884764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873313744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3873313744
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2374708935
Short name T614
Test name
Test status
Simulation time 318439932 ps
CPU time 9.96 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:53 PM PDT 24
Peak memory 198460 kb
Host smart-14f71182-b091-4c66-ab36-9d20bfdfd556
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374708935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2374708935
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.803250490
Short name T701
Test name
Test status
Simulation time 74354966 ps
CPU time 1.01 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 196732 kb
Host smart-9b34fc2d-aee6-4e81-ae19-4cbb6afc353c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803250490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.803250490
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.515724151
Short name T580
Test name
Test status
Simulation time 96806821 ps
CPU time 1.35 seconds
Started Aug 06 04:34:46 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 197584 kb
Host smart-19b2b7e5-8ff0-400e-b6ee-891551bc2e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515724151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.515724151
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2480398845
Short name T147
Test name
Test status
Simulation time 143650973 ps
CPU time 0.91 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 195940 kb
Host smart-46e218c6-7773-487a-b9c8-bc07e4f1f72e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480398845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2480398845
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1171061226
Short name T702
Test name
Test status
Simulation time 132263749 ps
CPU time 1.26 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:39 PM PDT 24
Peak memory 197288 kb
Host smart-47c8891a-f85c-4d03-994a-3a7f80b86155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171061226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1171061226
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2600372316
Short name T218
Test name
Test status
Simulation time 41827598 ps
CPU time 0.97 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:38 PM PDT 24
Peak memory 196440 kb
Host smart-dc75c74d-65ce-4b88-bc83-bb7eccb4cb7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600372316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2600372316
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.27497350
Short name T373
Test name
Test status
Simulation time 132836648 ps
CPU time 2.83 seconds
Started Aug 06 04:34:47 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 198440 kb
Host smart-731ce7b1-6461-4ebe-8b94-f4c33a88963b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27497350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand
om_long_reg_writes_reg_reads.27497350
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3016357581
Short name T536
Test name
Test status
Simulation time 215842461 ps
CPU time 1.06 seconds
Started Aug 06 04:34:21 PM PDT 24
Finished Aug 06 04:34:22 PM PDT 24
Peak memory 196224 kb
Host smart-fa0497a2-e67e-4e8c-ba60-2bcc54357884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016357581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3016357581
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.526643628
Short name T160
Test name
Test status
Simulation time 449711245 ps
CPU time 0.91 seconds
Started Aug 06 04:34:20 PM PDT 24
Finished Aug 06 04:34:21 PM PDT 24
Peak memory 196156 kb
Host smart-2d27bfb8-dbe9-446e-9289-a008abcf6617
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526643628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.526643628
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2845677438
Short name T439
Test name
Test status
Simulation time 6120972296 ps
CPU time 33.32 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:35:12 PM PDT 24
Peak memory 198620 kb
Host smart-2a215ceb-fad9-41f3-b7a5-86daff50d09d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845677438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2845677438
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3724847975
Short name T512
Test name
Test status
Simulation time 15898105 ps
CPU time 0.55 seconds
Started Aug 06 04:34:41 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 194312 kb
Host smart-1d6f5d47-88cd-41e2-976c-0e360b287255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724847975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3724847975
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.591668382
Short name T64
Test name
Test status
Simulation time 28377370 ps
CPU time 0.6 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:38 PM PDT 24
Peak memory 194356 kb
Host smart-aa257798-8ae8-4266-90b2-e2c646d5b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591668382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.591668382
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2359228972
Short name T527
Test name
Test status
Simulation time 760563002 ps
CPU time 14.5 seconds
Started Aug 06 04:35:06 PM PDT 24
Finished Aug 06 04:35:20 PM PDT 24
Peak memory 198376 kb
Host smart-24a84653-cc4d-4d2a-ac8e-51c30368e4db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359228972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2359228972
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1057632291
Short name T488
Test name
Test status
Simulation time 77182212 ps
CPU time 1.06 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 198364 kb
Host smart-67c5f1a4-ff06-4ba4-b38c-50aec746ed6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057632291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1057632291
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1664069334
Short name T426
Test name
Test status
Simulation time 38822975 ps
CPU time 0.81 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:46 PM PDT 24
Peak memory 195784 kb
Host smart-58038510-3527-45d3-a0bf-cfc925b9029c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664069334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1664069334
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3130463759
Short name T226
Test name
Test status
Simulation time 538166711 ps
CPU time 2.56 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 197020 kb
Host smart-039c2d58-a2a0-4b48-9f27-ebb9c3125ffb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130463759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3130463759
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1697011779
Short name T448
Test name
Test status
Simulation time 270217121 ps
CPU time 2.96 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 197368 kb
Host smart-833ab92e-da9c-4ff8-848d-4865d14d81b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697011779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1697011779
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3884647176
Short name T397
Test name
Test status
Simulation time 71488254 ps
CPU time 0.75 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 196536 kb
Host smart-359f0464-d443-4392-b6b3-33e35255043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884647176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3884647176
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2627131490
Short name T192
Test name
Test status
Simulation time 28519763 ps
CPU time 0.78 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 195716 kb
Host smart-64f49b6c-bb2e-4ae8-af8d-c097e4e7d5d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627131490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2627131490
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3737578515
Short name T673
Test name
Test status
Simulation time 91157217 ps
CPU time 3.9 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 198420 kb
Host smart-c39cd48f-5dee-4ef5-b02d-987fb3a48c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737578515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3737578515
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3450425183
Short name T327
Test name
Test status
Simulation time 68950204 ps
CPU time 0.9 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 196568 kb
Host smart-bf1f9f3b-0de8-410a-a84a-0fe50b9da791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450425183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3450425183
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.913327138
Short name T669
Test name
Test status
Simulation time 382236976 ps
CPU time 1.39 seconds
Started Aug 06 04:34:38 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 197284 kb
Host smart-040d72a3-c26c-4753-b8fb-20d1d1a97da5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913327138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.913327138
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.928760401
Short name T176
Test name
Test status
Simulation time 12412646790 ps
CPU time 161.58 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:37:19 PM PDT 24
Peak memory 198508 kb
Host smart-c06a42bd-e96f-4ba1-aee3-45793a0c7f64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928760401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.928760401
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1857417680
Short name T69
Test name
Test status
Simulation time 32137790 ps
CPU time 0.56 seconds
Started Aug 06 04:35:13 PM PDT 24
Finished Aug 06 04:35:14 PM PDT 24
Peak memory 194332 kb
Host smart-4c1e3579-1268-44ff-8109-82ac11ed2c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857417680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1857417680
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1503228619
Short name T345
Test name
Test status
Simulation time 90451247 ps
CPU time 0.83 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 196956 kb
Host smart-2bdb9cdb-2b37-4de4-989a-9f7ee01040c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503228619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1503228619
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2074424245
Short name T333
Test name
Test status
Simulation time 863732660 ps
CPU time 4.66 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 196360 kb
Host smart-3db23fdb-87b3-497a-8419-fa51c738d496
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074424245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2074424245
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1885644852
Short name T438
Test name
Test status
Simulation time 245587346 ps
CPU time 0.91 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 197472 kb
Host smart-dc75d261-22a1-4c61-9640-da5cabe277ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885644852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1885644852
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2561768148
Short name T149
Test name
Test status
Simulation time 20963598 ps
CPU time 0.65 seconds
Started Aug 06 04:34:50 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 195148 kb
Host smart-8930f9ef-dd35-452d-8200-287386ca0db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561768148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2561768148
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2310198477
Short name T547
Test name
Test status
Simulation time 40056439 ps
CPU time 1.53 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 196916 kb
Host smart-10bda122-797b-4430-acee-8f621e335569
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310198477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2310198477
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2967550380
Short name T445
Test name
Test status
Simulation time 271127091 ps
CPU time 2.07 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 196956 kb
Host smart-69997360-1787-4fdf-badc-f0ce1ec15373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967550380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2967550380
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.795891707
Short name T307
Test name
Test status
Simulation time 446197665 ps
CPU time 1.04 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 196352 kb
Host smart-c111a2f4-9b49-4e9c-8f30-6bf65834b1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795891707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.795891707
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4159835870
Short name T477
Test name
Test status
Simulation time 68849647 ps
CPU time 1.28 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 196920 kb
Host smart-b279fdc2-6425-407c-88d3-43857a35eebb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159835870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4159835870
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1894624491
Short name T524
Test name
Test status
Simulation time 94473585 ps
CPU time 1.44 seconds
Started Aug 06 04:34:42 PM PDT 24
Finished Aug 06 04:34:43 PM PDT 24
Peak memory 198368 kb
Host smart-df241097-a4df-4fde-85bd-97ddc4e59814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894624491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1894624491
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.661699974
Short name T156
Test name
Test status
Simulation time 461677382 ps
CPU time 1.09 seconds
Started Aug 06 04:34:42 PM PDT 24
Finished Aug 06 04:34:43 PM PDT 24
Peak memory 196812 kb
Host smart-700f3669-9477-4537-a3b2-ad717b5f862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661699974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.661699974
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.667690594
Short name T134
Test name
Test status
Simulation time 165595377 ps
CPU time 1.21 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:46 PM PDT 24
Peak memory 197240 kb
Host smart-2c4a4a2e-4439-49f2-881a-a46a86983c00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667690594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.667690594
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.121652531
Short name T621
Test name
Test status
Simulation time 29496572936 ps
CPU time 60.79 seconds
Started Aug 06 04:34:36 PM PDT 24
Finished Aug 06 04:35:37 PM PDT 24
Peak memory 198568 kb
Host smart-f276bb5a-96db-4b55-8fd6-d1d9cea1bafb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121652531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.121652531
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2813873247
Short name T510
Test name
Test status
Simulation time 48781285 ps
CPU time 0.6 seconds
Started Aug 06 04:34:41 PM PDT 24
Finished Aug 06 04:34:42 PM PDT 24
Peak memory 195240 kb
Host smart-f7814c50-9708-45cf-9300-ac632e75a02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813873247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2813873247
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.334631261
Short name T126
Test name
Test status
Simulation time 63919618 ps
CPU time 0.67 seconds
Started Aug 06 04:34:56 PM PDT 24
Finished Aug 06 04:34:57 PM PDT 24
Peak memory 196136 kb
Host smart-1bbba97c-c77c-42b0-a123-1ba4655eb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334631261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.334631261
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.19635143
Short name T472
Test name
Test status
Simulation time 2144592205 ps
CPU time 7.66 seconds
Started Aug 06 04:34:47 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 197436 kb
Host smart-19a56df5-ae9e-4972-8fe7-27c9ac283312
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stress
.19635143
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1315163964
Short name T490
Test name
Test status
Simulation time 71832976 ps
CPU time 0.67 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 194880 kb
Host smart-7b3c02ec-c2f9-449b-a34a-6936360bb7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315163964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1315163964
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1675846317
Short name T118
Test name
Test status
Simulation time 47420899 ps
CPU time 1.2 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:42 PM PDT 24
Peak memory 196376 kb
Host smart-fda42d38-082f-49ed-8eb2-34bbfa6a14c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675846317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1675846317
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1599959553
Short name T615
Test name
Test status
Simulation time 95177681 ps
CPU time 3.53 seconds
Started Aug 06 04:34:41 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 198348 kb
Host smart-aca1059d-d0e6-4b94-8c56-0b7c2dd7324c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599959553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1599959553
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3353773166
Short name T73
Test name
Test status
Simulation time 216622371 ps
CPU time 1.29 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 197096 kb
Host smart-36e0171b-5def-4fb0-b54c-5d97de1556d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353773166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3353773166
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2429965204
Short name T145
Test name
Test status
Simulation time 212744976 ps
CPU time 1.19 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 197284 kb
Host smart-5e73768d-636a-4ec5-8ac9-6a2c737e4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429965204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2429965204
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1615733599
Short name T325
Test name
Test status
Simulation time 33708827 ps
CPU time 1.19 seconds
Started Aug 06 04:34:50 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 196992 kb
Host smart-11089ad6-aa44-4dda-82a0-ff58f2655cee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615733599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1615733599
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3349363353
Short name T315
Test name
Test status
Simulation time 187768297 ps
CPU time 4.08 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 198436 kb
Host smart-881cc682-230c-4eb2-b67c-39b64bf90427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349363353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3349363353
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3019047810
Short name T660
Test name
Test status
Simulation time 461497034 ps
CPU time 1.23 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:39 PM PDT 24
Peak memory 197360 kb
Host smart-f860f23e-de7f-4840-80fe-070d2a49a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019047810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3019047810
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3443465332
Short name T705
Test name
Test status
Simulation time 365006280 ps
CPU time 1.35 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 197124 kb
Host smart-106ced48-6d89-429e-a108-b01ba551f012
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443465332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3443465332
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.411059243
Short name T229
Test name
Test status
Simulation time 8473032035 ps
CPU time 32.99 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:35:24 PM PDT 24
Peak memory 198448 kb
Host smart-1c690114-f78c-4c39-90ec-1076778e7614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411059243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.411059243
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.16787555
Short name T543
Test name
Test status
Simulation time 348093518468 ps
CPU time 321.16 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:39:58 PM PDT 24
Peak memory 198776 kb
Host smart-1cc0411a-d8c1-4b0b-b67b-bb8c89641813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=16787555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.16787555
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1772918259
Short name T515
Test name
Test status
Simulation time 28535968 ps
CPU time 0.55 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 195040 kb
Host smart-6b3c99b9-cb17-4743-83d3-24c804b0a32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772918259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1772918259
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1547951390
Short name T598
Test name
Test status
Simulation time 62849863 ps
CPU time 0.67 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 195544 kb
Host smart-c5021883-e920-4aeb-8431-fc9523a956ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547951390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1547951390
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.936553648
Short name T604
Test name
Test status
Simulation time 316980294 ps
CPU time 5.06 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 196376 kb
Host smart-7d95299e-3877-433a-9e45-fcefa543aa10
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936553648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.936553648
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1772262423
Short name T20
Test name
Test status
Simulation time 95725168 ps
CPU time 1.07 seconds
Started Aug 06 04:33:18 PM PDT 24
Finished Aug 06 04:33:19 PM PDT 24
Peak memory 197020 kb
Host smart-d9870527-98cf-4b52-bc68-e85b3f665039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772262423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1772262423
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1832503896
Short name T665
Test name
Test status
Simulation time 38282275 ps
CPU time 1.1 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 196292 kb
Host smart-ec57e4bd-23f7-4e53-a08f-a7e16f046735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832503896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1832503896
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.63121128
Short name T360
Test name
Test status
Simulation time 66629659 ps
CPU time 2.73 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 198496 kb
Host smart-03e010c6-f5af-4680-a796-1a1e502336db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63121128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.gpio_intr_with_filter_rand_intr_event.63121128
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3855129590
Short name T407
Test name
Test status
Simulation time 1165483235 ps
CPU time 3.09 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 196352 kb
Host smart-0d8e1783-657f-4c23-94b0-c8079eb04cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855129590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3855129590
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.109693343
Short name T613
Test name
Test status
Simulation time 128951531 ps
CPU time 1.26 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 196264 kb
Host smart-d895feb2-1d7a-4bb5-9fef-ab9d01a9b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109693343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.109693343
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2714002446
Short name T498
Test name
Test status
Simulation time 32452028 ps
CPU time 1.13 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 195748 kb
Host smart-36266be3-8d5d-4f2e-9c89-7f432781366e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714002446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2714002446
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3973939602
Short name T404
Test name
Test status
Simulation time 77790538 ps
CPU time 1.51 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 198412 kb
Host smart-cdd619dd-1b09-49f5-a37e-3dbd4cbe8ff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973939602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3973939602
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.538594117
Short name T32
Test name
Test status
Simulation time 81343077 ps
CPU time 0.83 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 214148 kb
Host smart-3955ab3e-29c9-4b09-ae42-49ee69a38bfc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538594117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.538594117
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1293023892
Short name T349
Test name
Test status
Simulation time 37778550 ps
CPU time 1.07 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 196188 kb
Host smart-11d51f88-125f-40e2-acf1-4d128c10cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293023892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1293023892
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.402708567
Short name T136
Test name
Test status
Simulation time 147895796 ps
CPU time 0.79 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 195676 kb
Host smart-5e93fd50-aa58-49e0-a393-ab7af621ce32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402708567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.402708567
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3019785801
Short name T348
Test name
Test status
Simulation time 26762262576 ps
CPU time 174.21 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:36:14 PM PDT 24
Peak memory 198472 kb
Host smart-3acbc8b3-5023-469d-9164-27441badb54b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019785801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3019785801
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2645201861
Short name T507
Test name
Test status
Simulation time 67922329703 ps
CPU time 268.75 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:37:50 PM PDT 24
Peak memory 198720 kb
Host smart-d03b5270-04e0-44fa-89ad-f6abb0bdff2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2645201861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2645201861
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.901467057
Short name T35
Test name
Test status
Simulation time 11650617 ps
CPU time 0.6 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:34:53 PM PDT 24
Peak memory 194352 kb
Host smart-6f1cc897-d5c3-4e36-8c7d-a19f22316d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901467057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.901467057
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.485908880
Short name T183
Test name
Test status
Simulation time 31707592 ps
CPU time 0.71 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 195464 kb
Host smart-2010035b-7b7d-4844-8703-1e3c457d77a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485908880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.485908880
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2920403403
Short name T493
Test name
Test status
Simulation time 843268533 ps
CPU time 11.64 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:57 PM PDT 24
Peak memory 195940 kb
Host smart-587f9558-8720-49fb-86c6-fd1df4be920a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920403403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2920403403
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.74730874
Short name T312
Test name
Test status
Simulation time 239535925 ps
CPU time 0.93 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 196752 kb
Host smart-5c8a974e-51b7-4d0c-9553-f594857b0450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74730874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.74730874
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.461418814
Short name T468
Test name
Test status
Simulation time 416982801 ps
CPU time 1.42 seconds
Started Aug 06 04:34:50 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 197300 kb
Host smart-adc4345a-61c3-4fb4-910e-cb418c69e137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461418814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.461418814
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3665124956
Short name T198
Test name
Test status
Simulation time 135442003 ps
CPU time 1.62 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 197316 kb
Host smart-e1979cac-0a1f-4f58-beca-59db752f3c59
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665124956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3665124956
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3719775249
Short name T323
Test name
Test status
Simulation time 90446223 ps
CPU time 0.89 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 195420 kb
Host smart-d308e01e-162d-4ec4-b24c-91c0a08065c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719775249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3719775249
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.401248911
Short name T391
Test name
Test status
Simulation time 26254647 ps
CPU time 0.72 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 195688 kb
Host smart-4734a577-b869-476d-9fc1-81209371ee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401248911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.401248911
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2656088459
Short name T370
Test name
Test status
Simulation time 50088371 ps
CPU time 0.79 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 195736 kb
Host smart-265c1df8-afa6-4e92-9d6d-b436a04015d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656088459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2656088459
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1974005324
Short name T628
Test name
Test status
Simulation time 130448014 ps
CPU time 1.75 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 198408 kb
Host smart-daad0be6-716a-4dc4-8795-361ecb1e46a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974005324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1974005324
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1270359257
Short name T381
Test name
Test status
Simulation time 173745431 ps
CPU time 1.3 seconds
Started Aug 06 04:34:37 PM PDT 24
Finished Aug 06 04:34:38 PM PDT 24
Peak memory 197352 kb
Host smart-5794e893-4e9e-46fe-89a3-6e59f6cc419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270359257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1270359257
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1331737717
Short name T220
Test name
Test status
Simulation time 29646472 ps
CPU time 0.93 seconds
Started Aug 06 04:34:36 PM PDT 24
Finished Aug 06 04:34:37 PM PDT 24
Peak memory 196132 kb
Host smart-81eadcc8-79d5-4dd8-bc7c-63dd73dd7952
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331737717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1331737717
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2116098438
Short name T291
Test name
Test status
Simulation time 1903493153 ps
CPU time 46.23 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:35:30 PM PDT 24
Peak memory 198500 kb
Host smart-0794d174-a7d6-4fbf-86df-ba721a2334aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116098438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2116098438
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.994975904
Short name T483
Test name
Test status
Simulation time 168241647177 ps
CPU time 1955.5 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 05:07:16 PM PDT 24
Peak memory 198772 kb
Host smart-81b23c3a-538e-4d2a-a624-646e76bbc495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=994975904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.994975904
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3027751190
Short name T455
Test name
Test status
Simulation time 21856294 ps
CPU time 0.58 seconds
Started Aug 06 04:35:12 PM PDT 24
Finished Aug 06 04:35:13 PM PDT 24
Peak memory 194576 kb
Host smart-3a9bb776-5cca-4929-bf72-ec60599c3295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027751190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3027751190
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1610884460
Short name T453
Test name
Test status
Simulation time 34952259 ps
CPU time 0.68 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 194340 kb
Host smart-41eab1ea-a30f-4030-a37c-fab40f866d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610884460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1610884460
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3432201741
Short name T263
Test name
Test status
Simulation time 3970311649 ps
CPU time 27.29 seconds
Started Aug 06 04:34:47 PM PDT 24
Finished Aug 06 04:35:14 PM PDT 24
Peak memory 197216 kb
Host smart-5b5f8d1e-d3be-424b-aa02-16ddd99e7083
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432201741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3432201741
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1796872449
Short name T658
Test name
Test status
Simulation time 315521815 ps
CPU time 1.04 seconds
Started Aug 06 04:35:11 PM PDT 24
Finished Aug 06 04:35:17 PM PDT 24
Peak memory 196892 kb
Host smart-41c41fb5-d911-4e2b-a6c2-7c58dbaffe8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796872449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1796872449
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2722324469
Short name T260
Test name
Test status
Simulation time 139227085 ps
CPU time 1.12 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 196092 kb
Host smart-30d3c523-17fd-4772-b4dd-d442cf79968d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722324469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2722324469
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.470554268
Short name T140
Test name
Test status
Simulation time 71079376 ps
CPU time 2.73 seconds
Started Aug 06 04:34:47 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 198604 kb
Host smart-65d6eb46-1fc4-4f82-b209-7724259d6812
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470554268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.470554268
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.530999697
Short name T395
Test name
Test status
Simulation time 99362828 ps
CPU time 0.88 seconds
Started Aug 06 04:34:46 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 195900 kb
Host smart-03884a1e-2bee-47c8-a47b-5238001a9e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530999697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
530999697
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2142654369
Short name T272
Test name
Test status
Simulation time 22943208 ps
CPU time 0.97 seconds
Started Aug 06 04:34:54 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 196484 kb
Host smart-1c7a0ed2-ff17-421c-8efa-81b4e16bbaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142654369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2142654369
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2661660807
Short name T470
Test name
Test status
Simulation time 58886466 ps
CPU time 0.75 seconds
Started Aug 06 04:35:10 PM PDT 24
Finished Aug 06 04:35:11 PM PDT 24
Peak memory 196492 kb
Host smart-6968793f-970f-4066-980e-5d1f2db02467
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661660807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2661660807
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2172730097
Short name T682
Test name
Test status
Simulation time 286952217 ps
CPU time 4.3 seconds
Started Aug 06 04:34:56 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 198424 kb
Host smart-918c4435-db0a-479b-9a14-8446c3895a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172730097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2172730097
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3779223412
Short name T357
Test name
Test status
Simulation time 39455381 ps
CPU time 1.2 seconds
Started Aug 06 04:34:41 PM PDT 24
Finished Aug 06 04:34:42 PM PDT 24
Peak memory 197372 kb
Host smart-c9eca32e-d277-4c5d-9875-afdb577b5655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779223412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3779223412
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.965492511
Short name T279
Test name
Test status
Simulation time 200913815 ps
CPU time 1.27 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 196308 kb
Host smart-ef84d7e1-d601-476a-a0c3-31ad35f32dca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965492511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.965492511
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3707352509
Short name T463
Test name
Test status
Simulation time 2240886887 ps
CPU time 26.21 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:35:10 PM PDT 24
Peak memory 198556 kb
Host smart-6d497bb0-3fa1-4e96-8423-72936326e858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707352509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3707352509
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1508278976
Short name T394
Test name
Test status
Simulation time 160895784440 ps
CPU time 1165.29 seconds
Started Aug 06 04:34:42 PM PDT 24
Finished Aug 06 04:54:07 PM PDT 24
Peak memory 198732 kb
Host smart-1631e0c8-b40d-4aec-8956-383a3f777627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1508278976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1508278976
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1674107023
Short name T45
Test name
Test status
Simulation time 135293044 ps
CPU time 0.58 seconds
Started Aug 06 04:35:16 PM PDT 24
Finished Aug 06 04:35:17 PM PDT 24
Peak memory 194420 kb
Host smart-1281972c-02da-4d8c-9766-13041b31678e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674107023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1674107023
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1885234913
Short name T231
Test name
Test status
Simulation time 43019232 ps
CPU time 0.63 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 194252 kb
Host smart-78fd2a75-48ff-458a-8f53-fa0db2d479bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885234913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1885234913
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3213820201
Short name T696
Test name
Test status
Simulation time 285391221 ps
CPU time 14.43 seconds
Started Aug 06 04:34:50 PM PDT 24
Finished Aug 06 04:35:05 PM PDT 24
Peak memory 197532 kb
Host smart-c8289a52-42ec-45fd-a8eb-c55eee8cfdce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213820201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3213820201
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4165105133
Short name T464
Test name
Test status
Simulation time 189700760 ps
CPU time 0.85 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:05 PM PDT 24
Peak memory 197080 kb
Host smart-c79e96bd-f167-4f4a-b8a6-e8e6ce29dd26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165105133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4165105133
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.577815051
Short name T298
Test name
Test status
Simulation time 67113713 ps
CPU time 1.01 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 196432 kb
Host smart-b8b3deb4-8f00-45fb-99f2-e85d15205626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577815051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.577815051
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1962302438
Short name T446
Test name
Test status
Simulation time 134825130 ps
CPU time 2.79 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 198584 kb
Host smart-31d5a34f-28d3-4238-a320-86ea61c74e3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962302438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1962302438
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3071972322
Short name T72
Test name
Test status
Simulation time 1510268173 ps
CPU time 2.51 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:47 PM PDT 24
Peak memory 196264 kb
Host smart-2433dd68-4da6-4682-b4f8-eeb363834c52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071972322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3071972322
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3370232267
Short name T497
Test name
Test status
Simulation time 194320553 ps
CPU time 1.04 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 197080 kb
Host smart-034c4f45-3e14-4e7a-91f1-638e85515065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370232267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3370232267
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3188241495
Short name T314
Test name
Test status
Simulation time 18942757 ps
CPU time 0.86 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:04 PM PDT 24
Peak memory 196804 kb
Host smart-50ab58d5-2dd9-4814-9f65-fe5f5d09909d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188241495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3188241495
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2028092866
Short name T10
Test name
Test status
Simulation time 256905147 ps
CPU time 3.36 seconds
Started Aug 06 04:35:18 PM PDT 24
Finished Aug 06 04:35:21 PM PDT 24
Peak memory 198436 kb
Host smart-c0262eec-250a-42d1-b865-658ef2377c4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028092866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2028092866
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3327374449
Short name T691
Test name
Test status
Simulation time 95021100 ps
CPU time 1.4 seconds
Started Aug 06 04:34:54 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 197212 kb
Host smart-e08f8821-e080-4289-b540-fb3fc4b6925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327374449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3327374449
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2116336834
Short name T693
Test name
Test status
Simulation time 315071980 ps
CPU time 0.87 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 195828 kb
Host smart-c184c9de-0f74-4135-a1cb-67a19c08560d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116336834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2116336834
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.369549429
Short name T280
Test name
Test status
Simulation time 20586691631 ps
CPU time 75.45 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:36:07 PM PDT 24
Peak memory 198632 kb
Host smart-a46561a8-d705-4328-b8b3-47d16105219d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369549429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.369549429
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.4245731212
Short name T54
Test name
Test status
Simulation time 387428315063 ps
CPU time 1653.14 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 05:02:17 PM PDT 24
Peak memory 198732 kb
Host smart-1d24a3e7-d954-4929-827d-08f3316d060f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4245731212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.4245731212
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1554803753
Short name T436
Test name
Test status
Simulation time 12120759 ps
CPU time 0.58 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 194308 kb
Host smart-d81fb919-7b11-42eb-a0b2-9d434088b05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554803753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1554803753
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3687213379
Short name T297
Test name
Test status
Simulation time 65726861 ps
CPU time 0.78 seconds
Started Aug 06 04:34:59 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 195768 kb
Host smart-1a256fe7-22fd-4547-a305-213c830fb53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687213379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3687213379
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3963737245
Short name T173
Test name
Test status
Simulation time 276085433 ps
CPU time 13.69 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:16 PM PDT 24
Peak memory 197416 kb
Host smart-845a7062-2e3d-445f-9ac6-87a7712f14bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963737245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3963737245
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3868975661
Short name T292
Test name
Test status
Simulation time 63175662 ps
CPU time 0.95 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 196560 kb
Host smart-5055a9f7-39bb-493b-97b3-8984763c5a72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868975661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3868975661
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3590199365
Short name T706
Test name
Test status
Simulation time 31203675 ps
CPU time 0.88 seconds
Started Aug 06 04:34:43 PM PDT 24
Finished Aug 06 04:34:44 PM PDT 24
Peak memory 196180 kb
Host smart-4e98dbb5-d9cc-43a7-9e79-8758dfe98718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590199365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3590199365
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3075361547
Short name T433
Test name
Test status
Simulation time 42570129 ps
CPU time 1.65 seconds
Started Aug 06 04:35:20 PM PDT 24
Finished Aug 06 04:35:21 PM PDT 24
Peak memory 197296 kb
Host smart-58e87b0d-776d-4ceb-bf63-4754c3269881
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075361547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3075361547
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4017073253
Short name T496
Test name
Test status
Simulation time 222202194 ps
CPU time 2.35 seconds
Started Aug 06 04:34:59 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 196376 kb
Host smart-81c5d817-ed27-4e22-bd4d-84b9c8431711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017073253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4017073253
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1436642501
Short name T585
Test name
Test status
Simulation time 56138620 ps
CPU time 1.13 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:05 PM PDT 24
Peak memory 196500 kb
Host smart-0a524c3e-8932-4b2c-8840-50c0137071d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436642501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1436642501
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3084692006
Short name T554
Test name
Test status
Simulation time 44192241 ps
CPU time 0.97 seconds
Started Aug 06 04:34:47 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 196960 kb
Host smart-257c921b-4886-4fb8-b02e-8ec0c037cc6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084692006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3084692006
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_smoke.3644413615
Short name T264
Test name
Test status
Simulation time 41759699 ps
CPU time 1.22 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 196892 kb
Host smart-641445ed-88ba-4b13-950f-64d94c23eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644413615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3644413615
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.526873156
Short name T413
Test name
Test status
Simulation time 168912798 ps
CPU time 0.81 seconds
Started Aug 06 04:35:15 PM PDT 24
Finished Aug 06 04:35:16 PM PDT 24
Peak memory 195768 kb
Host smart-09b8975e-ac0f-4ab6-bac0-dd343cfc875c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526873156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.526873156
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1554677478
Short name T486
Test name
Test status
Simulation time 17553613019 ps
CPU time 87.83 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:36:13 PM PDT 24
Peak memory 198616 kb
Host smart-49bba19e-d382-41b8-bf13-e4e58b5bd80b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554677478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1554677478
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2931206145
Short name T57
Test name
Test status
Simulation time 57345419889 ps
CPU time 1683.1 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 05:02:54 PM PDT 24
Peak memory 198712 kb
Host smart-827b2061-f137-499e-8867-3d230b69237b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2931206145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2931206145
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2689646046
Short name T34
Test name
Test status
Simulation time 13333198 ps
CPU time 0.6 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:41 PM PDT 24
Peak memory 194904 kb
Host smart-18885f77-59a7-49a4-ba15-62aa7efeb4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689646046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2689646046
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3713835886
Short name T503
Test name
Test status
Simulation time 24440851 ps
CPU time 0.71 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 195172 kb
Host smart-b9d790e9-38a0-436a-9a39-a5798a2f5927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713835886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3713835886
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1458665155
Short name T553
Test name
Test status
Simulation time 837364714 ps
CPU time 22.59 seconds
Started Aug 06 04:35:07 PM PDT 24
Finished Aug 06 04:35:30 PM PDT 24
Peak memory 197440 kb
Host smart-f703702c-c961-4941-a730-ca15522b0021
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458665155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1458665155
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.350462712
Short name T300
Test name
Test status
Simulation time 293135846 ps
CPU time 0.74 seconds
Started Aug 06 04:34:39 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 195012 kb
Host smart-2ee2ba22-945a-4343-8889-f939bfe6526d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350462712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.350462712
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1169556575
Short name T602
Test name
Test status
Simulation time 165889580 ps
CPU time 1.34 seconds
Started Aug 06 04:34:58 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 198572 kb
Host smart-cd633537-b730-48ba-b6cf-d9e47cc14ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169556575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1169556575
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2077405045
Short name T211
Test name
Test status
Simulation time 297263523 ps
CPU time 2.91 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 198552 kb
Host smart-928b7716-847d-4b0f-8b52-5453d88e0884
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077405045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2077405045
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3785493968
Short name T186
Test name
Test status
Simulation time 112750308 ps
CPU time 3.35 seconds
Started Aug 06 04:34:40 PM PDT 24
Finished Aug 06 04:34:43 PM PDT 24
Peak memory 197416 kb
Host smart-da98a936-9d76-4442-afa5-aa46a8132a7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785493968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3785493968
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.573138279
Short name T346
Test name
Test status
Simulation time 184797262 ps
CPU time 0.94 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:34:58 PM PDT 24
Peak memory 196232 kb
Host smart-84282583-7ae2-4057-b707-df68d63955bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573138279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.573138279
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1226540459
Short name T584
Test name
Test status
Simulation time 32436693 ps
CPU time 1.1 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 196308 kb
Host smart-48c331d0-63ce-4bd6-9b82-2e0b1855f74e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226540459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1226540459
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.977352765
Short name T237
Test name
Test status
Simulation time 30217853 ps
CPU time 1.34 seconds
Started Aug 06 04:34:41 PM PDT 24
Finished Aug 06 04:34:42 PM PDT 24
Peak memory 198268 kb
Host smart-8eb4ee13-2dfc-4411-bbb6-0ec65512a075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977352765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.977352765
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2642012903
Short name T504
Test name
Test status
Simulation time 201082278 ps
CPU time 0.85 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 195648 kb
Host smart-86139c30-14cf-415b-9652-543f054711a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642012903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2642012903
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3917646990
Short name T219
Test name
Test status
Simulation time 56500732 ps
CPU time 1.07 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:50 PM PDT 24
Peak memory 196004 kb
Host smart-8108f477-506e-4d1b-aaa9-1718cef420e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917646990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3917646990
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1947117974
Short name T429
Test name
Test status
Simulation time 46242882558 ps
CPU time 158.02 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:37:24 PM PDT 24
Peak memory 198524 kb
Host smart-75fd2b31-7fb5-4504-b855-82c75c3a982a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947117974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1947117974
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3588654628
Short name T55
Test name
Test status
Simulation time 57118505234 ps
CPU time 895.2 seconds
Started Aug 06 04:34:59 PM PDT 24
Finished Aug 06 04:49:55 PM PDT 24
Peak memory 198784 kb
Host smart-c2452258-a0cd-4291-a361-de84a82eec3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3588654628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3588654628
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.534719790
Short name T637
Test name
Test status
Simulation time 41393759 ps
CPU time 0.61 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:34:58 PM PDT 24
Peak memory 194224 kb
Host smart-087e9cfc-cb9d-41a9-8505-084dbbd3143d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534719790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.534719790
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3529153101
Short name T131
Test name
Test status
Simulation time 146513591 ps
CPU time 0.81 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:48 PM PDT 24
Peak memory 196580 kb
Host smart-96d71d47-12ed-4229-9222-cd2f6181997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529153101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3529153101
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3429997394
Short name T190
Test name
Test status
Simulation time 1049858731 ps
CPU time 26.09 seconds
Started Aug 06 04:34:54 PM PDT 24
Finished Aug 06 04:35:20 PM PDT 24
Peak memory 197360 kb
Host smart-a55fe9dc-936e-481d-9d74-b19c48795d68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429997394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3429997394
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1272047371
Short name T2
Test name
Test status
Simulation time 56801759 ps
CPU time 0.83 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 196160 kb
Host smart-4d92c179-0dbd-4803-8a67-319fa47932e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272047371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1272047371
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3844998880
Short name T529
Test name
Test status
Simulation time 89752082 ps
CPU time 0.99 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 196504 kb
Host smart-7a4c3869-f184-41cb-8563-3ead10ee8d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844998880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3844998880
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1459795276
Short name T683
Test name
Test status
Simulation time 187580516 ps
CPU time 3.36 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 198488 kb
Host smart-0b34f93b-b516-4432-acf3-79156a5de9de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459795276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1459795276
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.191167995
Short name T674
Test name
Test status
Simulation time 282724566 ps
CPU time 1.67 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 196876 kb
Host smart-6dc0b785-d52c-4ddb-8628-e441221284e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191167995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
191167995
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4015532127
Short name T437
Test name
Test status
Simulation time 100776542 ps
CPU time 0.99 seconds
Started Aug 06 04:34:45 PM PDT 24
Finished Aug 06 04:34:46 PM PDT 24
Peak memory 196400 kb
Host smart-2ad8540c-bfc3-4ce0-bcc5-b01f295d1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015532127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4015532127
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.497893755
Short name T401
Test name
Test status
Simulation time 26164334 ps
CPU time 0.72 seconds
Started Aug 06 04:34:50 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 195804 kb
Host smart-97e758cf-f18f-40a6-bdf3-79ededeaa4cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497893755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.497893755
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2409752073
Short name T714
Test name
Test status
Simulation time 372695449 ps
CPU time 3.45 seconds
Started Aug 06 04:34:58 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 198336 kb
Host smart-cf048c97-a05d-4a00-a5a5-e3124a9062c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409752073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2409752073
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4005633538
Short name T311
Test name
Test status
Simulation time 341165225 ps
CPU time 1.3 seconds
Started Aug 06 04:34:49 PM PDT 24
Finished Aug 06 04:34:51 PM PDT 24
Peak memory 197112 kb
Host smart-82e9b121-51d0-4212-bef0-2798ced3e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005633538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4005633538
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1949462690
Short name T228
Test name
Test status
Simulation time 230123008 ps
CPU time 1.21 seconds
Started Aug 06 04:34:44 PM PDT 24
Finished Aug 06 04:34:45 PM PDT 24
Peak memory 197204 kb
Host smart-0b03378a-02ed-442f-8d6b-82fa4d7e5578
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949462690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1949462690
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2726976141
Short name T374
Test name
Test status
Simulation time 37666554360 ps
CPU time 128.13 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:36:59 PM PDT 24
Peak memory 198584 kb
Host smart-91d8849b-c4e3-4262-8190-6df7295e86f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726976141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2726976141
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.133162227
Short name T172
Test name
Test status
Simulation time 21654387 ps
CPU time 0.59 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 194336 kb
Host smart-2e4dd92f-a938-46a5-a130-94752ea5c72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133162227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.133162227
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4125234010
Short name T14
Test name
Test status
Simulation time 137617626 ps
CPU time 0.77 seconds
Started Aug 06 04:35:01 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 195656 kb
Host smart-53c634ba-1990-4d92-b4ed-03dc376ed825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125234010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4125234010
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2868018961
Short name T508
Test name
Test status
Simulation time 3306036585 ps
CPU time 25.85 seconds
Started Aug 06 04:34:54 PM PDT 24
Finished Aug 06 04:35:20 PM PDT 24
Peak memory 197512 kb
Host smart-11535860-b901-4c5c-9a27-7ff0a702ad78
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868018961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2868018961
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4278138177
Short name T288
Test name
Test status
Simulation time 246065411 ps
CPU time 0.96 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 196988 kb
Host smart-a5cce9f6-4b5f-4cff-9803-9da2a4d2cb32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278138177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4278138177
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1690552251
Short name T148
Test name
Test status
Simulation time 57837269 ps
CPU time 0.96 seconds
Started Aug 06 04:34:54 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 196176 kb
Host smart-f4cbcb80-632c-4ca3-8aef-013b57fc0f7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690552251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1690552251
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2839783740
Short name T582
Test name
Test status
Simulation time 22026623 ps
CPU time 1.01 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:04 PM PDT 24
Peak memory 197440 kb
Host smart-8fa7a5be-7f11-456c-9ff2-28962af80450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839783740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2839783740
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3344869045
Short name T648
Test name
Test status
Simulation time 108444698 ps
CPU time 3.01 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:08 PM PDT 24
Peak memory 198444 kb
Host smart-2470fc84-5a0a-4c20-a958-037a85bb32e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344869045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3344869045
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3598835129
Short name T663
Test name
Test status
Simulation time 206238809 ps
CPU time 0.84 seconds
Started Aug 06 04:34:48 PM PDT 24
Finished Aug 06 04:34:49 PM PDT 24
Peak memory 195964 kb
Host smart-10937121-68f1-4db3-b6c6-4a760f50e32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598835129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3598835129
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.71520181
Short name T321
Test name
Test status
Simulation time 106730685 ps
CPU time 0.75 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 195824 kb
Host smart-48755829-2e1f-408a-97da-5e43bd69d2ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71520181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup_
pulldown.71520181
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.804078494
Short name T713
Test name
Test status
Simulation time 107214129 ps
CPU time 2.36 seconds
Started Aug 06 04:34:58 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 198388 kb
Host smart-01d67dbf-fae8-4189-84a9-dd4056811c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804078494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.804078494
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2791634351
Short name T697
Test name
Test status
Simulation time 72078299 ps
CPU time 1.14 seconds
Started Aug 06 04:35:08 PM PDT 24
Finished Aug 06 04:35:09 PM PDT 24
Peak memory 196824 kb
Host smart-04352e51-6333-413f-bdab-8bd03862346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791634351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2791634351
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2782853366
Short name T119
Test name
Test status
Simulation time 104669012 ps
CPU time 0.99 seconds
Started Aug 06 04:35:23 PM PDT 24
Finished Aug 06 04:35:24 PM PDT 24
Peak memory 196232 kb
Host smart-6fce0155-b7fc-4ddc-8217-a0a1d1f7853d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782853366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2782853366
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1498035771
Short name T606
Test name
Test status
Simulation time 10714482814 ps
CPU time 63.54 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:36:06 PM PDT 24
Peak memory 198608 kb
Host smart-0e748567-eef5-47e7-a0af-b88309b7c424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498035771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1498035771
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.766500641
Short name T53
Test name
Test status
Simulation time 36358244947 ps
CPU time 546.07 seconds
Started Aug 06 04:35:01 PM PDT 24
Finished Aug 06 04:44:07 PM PDT 24
Peak memory 198656 kb
Host smart-bca36c87-0fb7-4cc7-8e5b-7cba569d72fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=766500641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.766500641
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2245814766
Short name T667
Test name
Test status
Simulation time 25362433 ps
CPU time 0.56 seconds
Started Aug 06 04:34:51 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 194328 kb
Host smart-a2c8feac-f2db-4a6e-b127-81f7af0b8e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245814766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2245814766
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.989636816
Short name T416
Test name
Test status
Simulation time 34463117 ps
CPU time 0.6 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 194140 kb
Host smart-1b1b2bca-3c79-4a89-87c1-7c5ee3a51b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989636816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.989636816
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2634366193
Short name T152
Test name
Test status
Simulation time 195249011 ps
CPU time 7.01 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:11 PM PDT 24
Peak memory 197328 kb
Host smart-f36fd6d5-ddf2-4d74-9d39-ca5ed85fac2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634366193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2634366193
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2021493275
Short name T709
Test name
Test status
Simulation time 56564619 ps
CPU time 0.7 seconds
Started Aug 06 04:34:56 PM PDT 24
Finished Aug 06 04:34:57 PM PDT 24
Peak memory 195768 kb
Host smart-8c9ba73b-738b-4907-9d79-d1526245abf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021493275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2021493275
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.334772289
Short name T252
Test name
Test status
Simulation time 99921743 ps
CPU time 0.91 seconds
Started Aug 06 04:35:02 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 196916 kb
Host smart-58e7f8da-6b46-4d03-be13-8a6cd0fd89b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334772289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.334772289
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2518264179
Short name T611
Test name
Test status
Simulation time 65417556 ps
CPU time 0.88 seconds
Started Aug 06 04:35:25 PM PDT 24
Finished Aug 06 04:35:25 PM PDT 24
Peak memory 196552 kb
Host smart-fe1cad8c-16c7-41db-b95b-83435677d6c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518264179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2518264179
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.77580881
Short name T619
Test name
Test status
Simulation time 635112998 ps
CPU time 2.69 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 198456 kb
Host smart-7faa16f3-210f-487f-ae16-e8aa48f36a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77580881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.77580881
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.208254261
Short name T200
Test name
Test status
Simulation time 29348009 ps
CPU time 1.1 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:04 PM PDT 24
Peak memory 198512 kb
Host smart-130a748f-78dd-4a9d-ad11-ef79199d240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208254261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.208254261
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3574155090
Short name T262
Test name
Test status
Simulation time 74862837 ps
CPU time 0.78 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:34:52 PM PDT 24
Peak memory 196400 kb
Host smart-3d7a5c1c-36b8-43b6-8d35-5462a6bafe8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574155090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3574155090
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2320500617
Short name T540
Test name
Test status
Simulation time 24464584 ps
CPU time 1.18 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:34:59 PM PDT 24
Peak memory 197916 kb
Host smart-38d68439-4985-498d-85e7-fde8c82ae7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320500617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2320500617
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1455588159
Short name T420
Test name
Test status
Simulation time 119921564 ps
CPU time 1.18 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:55 PM PDT 24
Peak memory 195888 kb
Host smart-8179a85d-1c0f-49de-8fd2-44bda77ab507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455588159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1455588159
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1015784810
Short name T169
Test name
Test status
Simulation time 107339640 ps
CPU time 1.54 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 196180 kb
Host smart-c5ad7034-33b2-4706-9984-3bba7487cd0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015784810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1015784810
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1910992146
Short name T700
Test name
Test status
Simulation time 44221287182 ps
CPU time 119.72 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:36:57 PM PDT 24
Peak memory 198472 kb
Host smart-46f05d6c-22b2-489a-94f9-0bb55fc7f0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910992146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1910992146
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.856452421
Short name T521
Test name
Test status
Simulation time 12778035 ps
CPU time 0.56 seconds
Started Aug 06 04:35:08 PM PDT 24
Finished Aug 06 04:35:09 PM PDT 24
Peak memory 195088 kb
Host smart-3435b900-5b51-4861-b4f8-61dd55def94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856452421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.856452421
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3051557699
Short name T544
Test name
Test status
Simulation time 28722234 ps
CPU time 0.73 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 196272 kb
Host smart-9cc072ec-05ca-4a8d-b570-ca123bda7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051557699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3051557699
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3876317614
Short name T412
Test name
Test status
Simulation time 883721419 ps
CPU time 28.34 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:35:21 PM PDT 24
Peak memory 197196 kb
Host smart-2ce516b5-7ab5-49d5-a1d9-2dbafca8e401
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876317614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3876317614
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3585779439
Short name T232
Test name
Test status
Simulation time 253086643 ps
CPU time 0.93 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 04:34:54 PM PDT 24
Peak memory 197436 kb
Host smart-60f35828-7af6-405a-b8c3-7c1c637a67c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585779439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3585779439
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2341851660
Short name T189
Test name
Test status
Simulation time 44450451 ps
CPU time 0.87 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 196540 kb
Host smart-591581cc-f0c4-4fd8-b78d-e9929b60381b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341851660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2341851660
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1986843774
Short name T522
Test name
Test status
Simulation time 81254850 ps
CPU time 3.44 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:09 PM PDT 24
Peak memory 198512 kb
Host smart-bbe56ed8-13d7-48ae-a4c7-801de7e97442
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986843774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1986843774
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.904154856
Short name T480
Test name
Test status
Simulation time 83072615 ps
CPU time 2.35 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:07 PM PDT 24
Peak memory 198572 kb
Host smart-70adf295-ea57-4f99-a42e-ba941a2d34e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904154856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
904154856
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.330455327
Short name T400
Test name
Test status
Simulation time 33001530 ps
CPU time 0.89 seconds
Started Aug 06 04:35:01 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 196320 kb
Host smart-c6ec1f8b-a2dc-46ea-9cfb-b61bc92acc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330455327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.330455327
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.388437552
Short name T552
Test name
Test status
Simulation time 37952506 ps
CPU time 1 seconds
Started Aug 06 04:35:15 PM PDT 24
Finished Aug 06 04:35:16 PM PDT 24
Peak memory 196464 kb
Host smart-0b6cae5c-47c0-4fbf-9b1b-b631c30ca77d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388437552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.388437552
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1750269221
Short name T306
Test name
Test status
Simulation time 2272359528 ps
CPU time 5.37 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:35:02 PM PDT 24
Peak memory 198500 kb
Host smart-4caccff6-8499-496b-afd2-ee9be4abc72c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750269221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1750269221
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2070553607
Short name T698
Test name
Test status
Simulation time 80390231 ps
CPU time 1 seconds
Started Aug 06 04:35:27 PM PDT 24
Finished Aug 06 04:35:28 PM PDT 24
Peak memory 196856 kb
Host smart-5e7dabe0-5789-45bf-b691-ad7938cf6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070553607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2070553607
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.412890728
Short name T622
Test name
Test status
Simulation time 31487720 ps
CPU time 1.03 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:04 PM PDT 24
Peak memory 196100 kb
Host smart-ef1f2aff-8e5e-4549-8236-2f12f422d33a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412890728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.412890728
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2778679083
Short name T564
Test name
Test status
Simulation time 42838342917 ps
CPU time 111.43 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:36:43 PM PDT 24
Peak memory 198568 kb
Host smart-7aa22cab-1524-495f-a9c5-d9b48e0a2fac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778679083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2778679083
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.48808662
Short name T46
Test name
Test status
Simulation time 40243252 ps
CPU time 0.56 seconds
Started Aug 06 04:35:05 PM PDT 24
Finished Aug 06 04:35:06 PM PDT 24
Peak memory 194428 kb
Host smart-f88eefbd-8fbd-40eb-b4c7-72b17b00ca7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48808662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.48808662
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1113078828
Short name T451
Test name
Test status
Simulation time 51971216 ps
CPU time 0.95 seconds
Started Aug 06 04:34:52 PM PDT 24
Finished Aug 06 04:34:53 PM PDT 24
Peak memory 196296 kb
Host smart-1820e2e1-d176-4a17-b1c8-c9b9022fb32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113078828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1113078828
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.239893047
Short name T257
Test name
Test status
Simulation time 598847266 ps
CPU time 7.47 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:12 PM PDT 24
Peak memory 197368 kb
Host smart-8b2a1a20-850e-404a-83e8-f8187208fa93
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239893047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.239893047
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3224540015
Short name T202
Test name
Test status
Simulation time 54858983 ps
CPU time 0.92 seconds
Started Aug 06 04:35:00 PM PDT 24
Finished Aug 06 04:35:01 PM PDT 24
Peak memory 197652 kb
Host smart-a43d87ce-fa9f-41ae-b526-b41bbb4a9627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224540015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3224540015
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1123218527
Short name T703
Test name
Test status
Simulation time 95191631 ps
CPU time 1.35 seconds
Started Aug 06 04:34:57 PM PDT 24
Finished Aug 06 04:34:59 PM PDT 24
Peak memory 197480 kb
Host smart-cf3dd247-4f82-404b-ae68-0610bc119ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123218527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1123218527
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3107401599
Short name T165
Test name
Test status
Simulation time 98203825 ps
CPU time 3.68 seconds
Started Aug 06 04:35:04 PM PDT 24
Finished Aug 06 04:35:08 PM PDT 24
Peak memory 196656 kb
Host smart-103f8516-2ecd-47ad-95e4-7fdffd07e3a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107401599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3107401599
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1526418042
Short name T162
Test name
Test status
Simulation time 275334805 ps
CPU time 1.95 seconds
Started Aug 06 04:34:58 PM PDT 24
Finished Aug 06 04:35:00 PM PDT 24
Peak memory 197924 kb
Host smart-925db478-9a9c-4442-ab26-d47d43a3ea15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526418042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1526418042
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.273841440
Short name T117
Test name
Test status
Simulation time 61919915 ps
CPU time 0.66 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:03 PM PDT 24
Peak memory 195452 kb
Host smart-1e5cb1be-5c08-4e48-8f84-be13ca4209c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273841440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.273841440
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.196596813
Short name T241
Test name
Test status
Simulation time 72764168 ps
CPU time 0.85 seconds
Started Aug 06 04:35:00 PM PDT 24
Finished Aug 06 04:35:01 PM PDT 24
Peak memory 197044 kb
Host smart-b0e1c4ff-a975-448b-ba7f-f0a06b8b2913
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196596813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.196596813
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.800697479
Short name T542
Test name
Test status
Simulation time 191019759 ps
CPU time 2.4 seconds
Started Aug 06 04:35:43 PM PDT 24
Finished Aug 06 04:35:45 PM PDT 24
Peak memory 198384 kb
Host smart-06f0233a-bf1d-4644-b7bf-287a5cb2da1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800697479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.800697479
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.399694344
Short name T368
Test name
Test status
Simulation time 65511397 ps
CPU time 1.05 seconds
Started Aug 06 04:35:07 PM PDT 24
Finished Aug 06 04:35:08 PM PDT 24
Peak memory 196224 kb
Host smart-ca6ed176-3909-4c05-8c20-22558f79ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399694344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.399694344
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.4281078602
Short name T460
Test name
Test status
Simulation time 23790145 ps
CPU time 0.78 seconds
Started Aug 06 04:35:03 PM PDT 24
Finished Aug 06 04:35:04 PM PDT 24
Peak memory 195544 kb
Host smart-f461bafa-b1ff-44bc-b592-67d0b8327ff9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281078602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.4281078602
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4068132691
Short name T258
Test name
Test status
Simulation time 26231766816 ps
CPU time 75.55 seconds
Started Aug 06 04:35:19 PM PDT 24
Finished Aug 06 04:36:35 PM PDT 24
Peak memory 198584 kb
Host smart-ff0c618d-b6cc-4298-95f7-6772849de6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068132691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4068132691
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1240073370
Short name T635
Test name
Test status
Simulation time 161201276230 ps
CPU time 1895.31 seconds
Started Aug 06 04:34:53 PM PDT 24
Finished Aug 06 05:06:28 PM PDT 24
Peak memory 198664 kb
Host smart-673d3125-36dd-4a75-be50-e24693c6bd54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1240073370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1240073370
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2193030615
Short name T47
Test name
Test status
Simulation time 12613228 ps
CPU time 0.54 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 193120 kb
Host smart-2758fc31-6163-47fa-b1cc-64cc9fd5d6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193030615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2193030615
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4178379681
Short name T539
Test name
Test status
Simulation time 23967124 ps
CPU time 0.73 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 196388 kb
Host smart-821c6756-9699-42a5-99ed-4aced03716be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178379681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4178379681
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.284900849
Short name T505
Test name
Test status
Simulation time 322888492 ps
CPU time 8.67 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 197304 kb
Host smart-13764a7c-3ec5-4e97-aa31-b942ac581add
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284900849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.284900849
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3094255581
Short name T695
Test name
Test status
Simulation time 331656044 ps
CPU time 0.98 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196788 kb
Host smart-f510cc87-a962-4d92-961a-f3ece3740d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094255581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3094255581
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.620252862
Short name T523
Test name
Test status
Simulation time 162790790 ps
CPU time 1.28 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 198512 kb
Host smart-de03b232-963d-4bae-884b-77e1d900d06a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620252862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.620252862
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1116002603
Short name T216
Test name
Test status
Simulation time 170563171 ps
CPU time 1.74 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 198328 kb
Host smart-945fab85-1b70-475b-afc5-7d70dd4b634b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116002603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1116002603
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2195743054
Short name T657
Test name
Test status
Simulation time 233012279 ps
CPU time 2.37 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 198428 kb
Host smart-faccdf1d-dd63-488c-9f26-714c9e8db4cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195743054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2195743054
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1775847344
Short name T364
Test name
Test status
Simulation time 72136303 ps
CPU time 1.31 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 197448 kb
Host smart-38fcf5db-81c7-46a2-a913-9d8f5d45aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775847344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1775847344
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4292974215
Short name T193
Test name
Test status
Simulation time 41636879 ps
CPU time 1.21 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 196452 kb
Host smart-db6dca41-4aa8-4366-9c49-3c2f838c56a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292974215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4292974215
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1196396234
Short name T319
Test name
Test status
Simulation time 824151168 ps
CPU time 3.24 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 198388 kb
Host smart-5e3919d9-857b-4e49-b915-8f426ccdca4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196396234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1196396234
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1373869059
Short name T424
Test name
Test status
Simulation time 29650467 ps
CPU time 0.83 seconds
Started Aug 06 04:33:18 PM PDT 24
Finished Aug 06 04:33:19 PM PDT 24
Peak memory 196612 kb
Host smart-05bc5dea-fd47-43a2-8758-8e3fafbe6b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373869059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1373869059
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3540792114
Short name T560
Test name
Test status
Simulation time 97683122 ps
CPU time 1.39 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 197184 kb
Host smart-ef8983dd-a53f-484e-bfdb-269418fb1c1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540792114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3540792114
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1913941641
Short name T562
Test name
Test status
Simulation time 67008537791 ps
CPU time 77.71 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:34:40 PM PDT 24
Peak memory 192484 kb
Host smart-801d370c-bd43-4fd1-b952-0275c92f002e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913941641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1913941641
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2046113037
Short name T58
Test name
Test status
Simulation time 110668467889 ps
CPU time 1377.84 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:56:17 PM PDT 24
Peak memory 198724 kb
Host smart-281edf32-f97b-4307-ab5e-413994aa0e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2046113037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2046113037
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.804733059
Short name T375
Test name
Test status
Simulation time 21871957 ps
CPU time 0.56 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 194240 kb
Host smart-52ab747d-28fe-476a-add6-1a4831d589f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804733059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.804733059
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1344909794
Short name T267
Test name
Test status
Simulation time 28544683 ps
CPU time 0.85 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 196796 kb
Host smart-4fe89fd2-6c2c-44ef-9cf1-23755d41f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344909794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1344909794
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1684917516
Short name T434
Test name
Test status
Simulation time 360512889 ps
CPU time 8.18 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 196824 kb
Host smart-217e0276-3d89-487e-ab24-ff262a20c2e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684917516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1684917516
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2601079442
Short name T548
Test name
Test status
Simulation time 269161603 ps
CPU time 0.92 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 197484 kb
Host smart-ccc7e302-dd18-4808-b5f4-763b31a2d0ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601079442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2601079442
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3600010418
Short name T600
Test name
Test status
Simulation time 17811007 ps
CPU time 0.7 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:19 PM PDT 24
Peak memory 194848 kb
Host smart-b82e7cbf-3c14-440e-8bd7-93729d32a4dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600010418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3600010418
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.212845552
Short name T634
Test name
Test status
Simulation time 128723360 ps
CPU time 1.44 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 196832 kb
Host smart-44179c76-60ff-4a51-8237-dd5526148caa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212845552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.212845552
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1104528176
Short name T618
Test name
Test status
Simulation time 173139997 ps
CPU time 1.43 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 197296 kb
Host smart-f7a69e8a-8ef4-456c-80da-28a9b803a572
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104528176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1104528176
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1581909998
Short name T487
Test name
Test status
Simulation time 38619042 ps
CPU time 0.97 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 196412 kb
Host smart-6bcc70a7-b17d-4351-be60-f940c74809c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581909998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1581909998
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2020545678
Short name T106
Test name
Test status
Simulation time 59017614 ps
CPU time 0.72 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 195772 kb
Host smart-d30b48d6-e3cc-4e82-a927-b2b403ff1bd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020545678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2020545678
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3881068361
Short name T326
Test name
Test status
Simulation time 251054104 ps
CPU time 5.43 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 198424 kb
Host smart-cae9a0bb-6d05-4742-901c-3e0ce4fc8c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881068361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3881068361
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3090976368
Short name T419
Test name
Test status
Simulation time 101420067 ps
CPU time 1.01 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:33:21 PM PDT 24
Peak memory 196072 kb
Host smart-b27635a2-f75e-4a6a-86b1-3e31faaf2b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090976368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3090976368
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3067070242
Short name T511
Test name
Test status
Simulation time 232298200 ps
CPU time 0.97 seconds
Started Aug 06 04:33:18 PM PDT 24
Finished Aug 06 04:33:19 PM PDT 24
Peak memory 196228 kb
Host smart-f7e9ef05-f3aa-46b8-abbd-c7c44b8f338d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067070242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3067070242
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4046830773
Short name T380
Test name
Test status
Simulation time 57452758879 ps
CPU time 182.7 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:36:25 PM PDT 24
Peak memory 198600 kb
Host smart-b8267ea7-f433-4cb4-b5de-cb3299e467e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046830773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4046830773
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1115294772
Short name T550
Test name
Test status
Simulation time 224345093815 ps
CPU time 1363.2 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:56:03 PM PDT 24
Peak memory 198608 kb
Host smart-af544820-f931-43ab-98f2-2502ac21ed3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1115294772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1115294772
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.120454794
Short name T588
Test name
Test status
Simulation time 15603176 ps
CPU time 0.56 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 194156 kb
Host smart-94328d9d-e481-4388-8670-cedc05d3b5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120454794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.120454794
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4199979059
Short name T347
Test name
Test status
Simulation time 60890678 ps
CPU time 0.81 seconds
Started Aug 06 04:33:19 PM PDT 24
Finished Aug 06 04:33:20 PM PDT 24
Peak memory 195488 kb
Host smart-9bd9ef77-fcf1-4127-9c14-48779520799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199979059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4199979059
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2433755819
Short name T205
Test name
Test status
Simulation time 1232128771 ps
CPU time 15.25 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:38 PM PDT 24
Peak memory 198452 kb
Host smart-125e2733-c4ce-4b43-89ed-f2376d39a157
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433755819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2433755819
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2592286734
Short name T388
Test name
Test status
Simulation time 686316640 ps
CPU time 0.97 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 197096 kb
Host smart-40283578-85e1-4e4b-9cfe-0236d3e1b0d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592286734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2592286734
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.802656832
Short name T179
Test name
Test status
Simulation time 81149472 ps
CPU time 1.27 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 197320 kb
Host smart-20796326-f10d-4550-b78f-4a99ba2b0f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802656832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.802656832
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2185820977
Short name T301
Test name
Test status
Simulation time 331790104 ps
CPU time 3.18 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 198604 kb
Host smart-2dddf12c-2d8c-4ecc-a9e0-8d836d54cf69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185820977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2185820977
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1769662983
Short name T155
Test name
Test status
Simulation time 346622347 ps
CPU time 2.58 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:26 PM PDT 24
Peak memory 197748 kb
Host smart-4e3ad513-4789-4896-b595-009fe616ac4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769662983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1769662983
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2879198720
Short name T277
Test name
Test status
Simulation time 22685400 ps
CPU time 0.71 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196556 kb
Host smart-d7c0d655-2f00-486f-b4fc-5b6660368b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879198720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2879198720
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.388004806
Short name T17
Test name
Test status
Simulation time 61442551 ps
CPU time 1.26 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 197548 kb
Host smart-247a68b9-c631-46e2-8d20-3fe0dd4dbd1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388004806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.388004806
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3546827661
Short name T21
Test name
Test status
Simulation time 122938165 ps
CPU time 1.69 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 198416 kb
Host smart-29a9bb12-b870-44b2-8555-86ccade4dc3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546827661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3546827661
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2925370799
Short name T154
Test name
Test status
Simulation time 58868332 ps
CPU time 1.02 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 195860 kb
Host smart-d50b56a2-9506-4e07-a3a3-0775cf058976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925370799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2925370799
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1685447903
Short name T414
Test name
Test status
Simulation time 47750644 ps
CPU time 0.93 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 197588 kb
Host smart-823cdc6b-11f0-4e42-a9b9-658eb8e94233
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685447903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1685447903
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2565924242
Short name T501
Test name
Test status
Simulation time 2778343286 ps
CPU time 52.15 seconds
Started Aug 06 04:33:20 PM PDT 24
Finished Aug 06 04:34:13 PM PDT 24
Peak memory 198588 kb
Host smart-0bda936d-f95b-4a03-9338-b583fffde305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565924242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2565924242
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1457233669
Short name T586
Test name
Test status
Simulation time 60296741609 ps
CPU time 1452.64 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:57:34 PM PDT 24
Peak memory 198612 kb
Host smart-273ae7d6-2669-4d0d-b832-c67415fe60b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1457233669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1457233669
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1406741433
Short name T587
Test name
Test status
Simulation time 17002394 ps
CPU time 0.55 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 194220 kb
Host smart-d266ab20-41e0-49ce-985b-694b9e94724a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406741433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1406741433
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4114714649
Short name T454
Test name
Test status
Simulation time 16333820 ps
CPU time 0.64 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 194476 kb
Host smart-9e9cc6e9-87ab-4c81-9e53-2ab4261cf50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114714649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4114714649
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4008560278
Short name T302
Test name
Test status
Simulation time 1246519992 ps
CPU time 17.6 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:44 PM PDT 24
Peak memory 198320 kb
Host smart-de907f2d-95bd-430a-b400-ebccd5e0f958
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008560278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4008560278
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.445389607
Short name T473
Test name
Test status
Simulation time 30057450 ps
CPU time 0.68 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:26 PM PDT 24
Peak memory 195884 kb
Host smart-81971f4f-a86c-4746-afb8-664fc5facf2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445389607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.445389607
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3763065326
Short name T494
Test name
Test status
Simulation time 18176660 ps
CPU time 0.71 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 194664 kb
Host smart-5c513a69-14b0-45f2-afc8-e13ba544fd47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763065326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3763065326
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1752162432
Short name T599
Test name
Test status
Simulation time 122158235 ps
CPU time 1.25 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 197180 kb
Host smart-ad756426-02e7-4464-a001-4558f25fb071
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752162432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1752162432
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1193581839
Short name T408
Test name
Test status
Simulation time 681632236 ps
CPU time 1.61 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 196612 kb
Host smart-4286d932-84f6-48cb-9428-1ceb75465d76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193581839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1193581839
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3527523726
Short name T157
Test name
Test status
Simulation time 28321089 ps
CPU time 0.8 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 195852 kb
Host smart-97b9ff18-2729-46a4-9eaf-d4d167947715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527523726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3527523726
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.4164291559
Short name T320
Test name
Test status
Simulation time 34377833 ps
CPU time 1.19 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196284 kb
Host smart-49dab5f0-c58d-4b94-abe3-f6fb6f0088be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164291559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.4164291559
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1573648824
Short name T71
Test name
Test status
Simulation time 488833169 ps
CPU time 2.22 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 198504 kb
Host smart-455d121f-a9f4-4022-a4f6-da7ccfd5252b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573648824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1573648824
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1049929729
Short name T431
Test name
Test status
Simulation time 335996594 ps
CPU time 0.95 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196244 kb
Host smart-8772b4d7-44a2-4e4e-8e9a-7345531ba215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049929729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1049929729
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3510948197
Short name T390
Test name
Test status
Simulation time 98968166 ps
CPU time 0.93 seconds
Started Aug 06 04:33:21 PM PDT 24
Finished Aug 06 04:33:22 PM PDT 24
Peak memory 196004 kb
Host smart-1cb10f5e-e119-44d1-a1dd-aa8c20db35e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510948197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3510948197
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3723795462
Short name T230
Test name
Test status
Simulation time 21483694276 ps
CPU time 126.67 seconds
Started Aug 06 04:33:25 PM PDT 24
Finished Aug 06 04:35:32 PM PDT 24
Peak memory 198660 kb
Host smart-956b62da-9738-4600-9e89-8c3393b8d862
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723795462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3723795462
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.106737215
Short name T278
Test name
Test status
Simulation time 199885170 ps
CPU time 0.58 seconds
Started Aug 06 04:33:34 PM PDT 24
Finished Aug 06 04:33:35 PM PDT 24
Peak memory 195220 kb
Host smart-6905be48-acfd-4481-9374-588d4d75e87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106737215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.106737215
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2463772929
Short name T495
Test name
Test status
Simulation time 101057263 ps
CPU time 0.8 seconds
Started Aug 06 04:33:27 PM PDT 24
Finished Aug 06 04:33:28 PM PDT 24
Peak memory 196976 kb
Host smart-e871a905-26ea-4a25-85f3-c9aba34af469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463772929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2463772929
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2054032551
Short name T668
Test name
Test status
Simulation time 683990511 ps
CPU time 5.84 seconds
Started Aug 06 04:33:33 PM PDT 24
Finished Aug 06 04:33:39 PM PDT 24
Peak memory 197240 kb
Host smart-7492a32a-467c-49a1-942c-bc78fec8fbfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054032551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2054032551
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3567312489
Short name T354
Test name
Test status
Simulation time 90965800 ps
CPU time 0.83 seconds
Started Aug 06 04:33:31 PM PDT 24
Finished Aug 06 04:33:32 PM PDT 24
Peak memory 197032 kb
Host smart-4a088164-4d82-453f-8cb0-72bc24edd202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567312489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3567312489
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3376562598
Short name T313
Test name
Test status
Simulation time 463567936 ps
CPU time 1.35 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 197320 kb
Host smart-0e5f034b-7b83-4be9-95b4-61311e48dd4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376562598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3376562598
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3435443840
Short name T114
Test name
Test status
Simulation time 85473285 ps
CPU time 2.96 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:29 PM PDT 24
Peak memory 198564 kb
Host smart-cec8e339-f4a4-4ee2-995c-bd8bc69cc997
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435443840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3435443840
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.376610636
Short name T651
Test name
Test status
Simulation time 109091243 ps
CPU time 1.35 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196140 kb
Host smart-5c7f2b55-004f-4242-867a-d9e2d4f124bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376610636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.376610636
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3068222612
Short name T707
Test name
Test status
Simulation time 32740649 ps
CPU time 1.15 seconds
Started Aug 06 04:33:22 PM PDT 24
Finished Aug 06 04:33:23 PM PDT 24
Peak memory 197428 kb
Host smart-63085ed0-a099-4185-bee8-2aadf8a16dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068222612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3068222612
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1040431873
Short name T125
Test name
Test status
Simulation time 134606272 ps
CPU time 1.21 seconds
Started Aug 06 04:33:23 PM PDT 24
Finished Aug 06 04:33:24 PM PDT 24
Peak memory 197272 kb
Host smart-92031893-67ab-4df9-95e9-2ee09c2b25e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040431873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1040431873
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1130446494
Short name T655
Test name
Test status
Simulation time 727899692 ps
CPU time 5.59 seconds
Started Aug 06 04:33:29 PM PDT 24
Finished Aug 06 04:33:34 PM PDT 24
Peak memory 198428 kb
Host smart-a6cd3511-b390-47dd-83df-18d507bce3e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130446494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1130446494
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1222771267
Short name T518
Test name
Test status
Simulation time 116258867 ps
CPU time 0.94 seconds
Started Aug 06 04:33:26 PM PDT 24
Finished Aug 06 04:33:27 PM PDT 24
Peak memory 196904 kb
Host smart-40b6a171-4fe8-4150-9bc6-c2cbda0ff040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222771267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1222771267
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3266783773
Short name T171
Test name
Test status
Simulation time 46599285 ps
CPU time 0.88 seconds
Started Aug 06 04:33:24 PM PDT 24
Finished Aug 06 04:33:25 PM PDT 24
Peak memory 196460 kb
Host smart-ac749f32-5b2a-4033-ba6e-abea017e0b30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266783773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3266783773
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3106178433
Short name T206
Test name
Test status
Simulation time 12265934954 ps
CPU time 159.46 seconds
Started Aug 06 04:33:36 PM PDT 24
Finished Aug 06 04:36:16 PM PDT 24
Peak memory 198664 kb
Host smart-3653d41f-83f5-4911-ba38-f1cf61869acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106178433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3106178433
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2877312008
Short name T852
Test name
Test status
Simulation time 115597971 ps
CPU time 1.06 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196372 kb
Host smart-12b6e14a-b6bb-4ab9-a189-a8211101fe62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2877312008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2877312008
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844591822
Short name T897
Test name
Test status
Simulation time 411399035 ps
CPU time 1.41 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196564 kb
Host smart-6dbaf187-b5aa-472c-a0fb-50182de63ac6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844591822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1844591822
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3837042821
Short name T915
Test name
Test status
Simulation time 54733279 ps
CPU time 1.09 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 197660 kb
Host smart-20b1d4ef-8c04-4572-b27b-98269da78a8e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3837042821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3837042821
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642722602
Short name T858
Test name
Test status
Simulation time 148814813 ps
CPU time 0.9 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 195428 kb
Host smart-24da680b-069b-44f0-8a79-381a31afcd02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642722602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1642722602
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1806703180
Short name T933
Test name
Test status
Simulation time 166388754 ps
CPU time 0.96 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196232 kb
Host smart-8c1fb550-f001-460f-bb1b-08eafc0b4258
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1806703180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1806703180
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1049666775
Short name T901
Test name
Test status
Simulation time 100804750 ps
CPU time 0.96 seconds
Started Aug 06 04:32:46 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 196500 kb
Host smart-67885fe9-7c71-48f2-b34d-311fb4027fd0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049666775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1049666775
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.52874869
Short name T946
Test name
Test status
Simulation time 27961123 ps
CPU time 0.87 seconds
Started Aug 06 04:32:46 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 195904 kb
Host smart-a02c5338-e841-4171-a361-ee318c55efb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=52874869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.52874869
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.81347607
Short name T878
Test name
Test status
Simulation time 90789001 ps
CPU time 1.3 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196644 kb
Host smart-df5c2166-d695-41be-8625-10d2160bb1fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81347607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.81347607
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1038133203
Short name T936
Test name
Test status
Simulation time 61101166 ps
CPU time 0.95 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197140 kb
Host smart-679c80c6-ff50-4e52-a13a-9bad70517c15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1038133203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1038133203
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4076829518
Short name T934
Test name
Test status
Simulation time 45781831 ps
CPU time 0.94 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 197792 kb
Host smart-a85bceb7-92cb-4d16-b975-f161bd0b96ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076829518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4076829518
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.719354735
Short name T848
Test name
Test status
Simulation time 582894722 ps
CPU time 1.18 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197176 kb
Host smart-7df1889f-055d-473e-a0cb-a2dc7343dc42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=719354735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.719354735
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4148711005
Short name T937
Test name
Test status
Simulation time 28494304 ps
CPU time 0.84 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196084 kb
Host smart-7d22de32-9e73-4bfe-978f-c0bfb1604637
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148711005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4148711005
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3998445207
Short name T921
Test name
Test status
Simulation time 184481901 ps
CPU time 0.99 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196292 kb
Host smart-59da8a84-8bed-4cbc-bbca-9dc4a535386e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3998445207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3998445207
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1997381065
Short name T888
Test name
Test status
Simulation time 43743103 ps
CPU time 1.05 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197852 kb
Host smart-3ee4a92e-0b3c-4400-8820-9d3de0c7686c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997381065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1997381065
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2662226257
Short name T892
Test name
Test status
Simulation time 143832721 ps
CPU time 0.96 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 197824 kb
Host smart-a03d2ed8-f30a-45ab-bfd8-9557f030bfd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2662226257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2662226257
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887820127
Short name T913
Test name
Test status
Simulation time 277350139 ps
CPU time 1.27 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 196360 kb
Host smart-effe61af-6399-46b2-9d6a-96fcca761f84
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887820127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2887820127
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1845181304
Short name T869
Test name
Test status
Simulation time 89546435 ps
CPU time 1.27 seconds
Started Aug 06 04:32:37 PM PDT 24
Finished Aug 06 04:32:39 PM PDT 24
Peak memory 196500 kb
Host smart-07499a89-b0a5-4e72-a0b1-5a1c9128f08b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1845181304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1845181304
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3534117274
Short name T926
Test name
Test status
Simulation time 133712211 ps
CPU time 1.2 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196164 kb
Host smart-e61dfaa2-44a8-4553-809d-947e331f3c9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534117274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3534117274
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.332112020
Short name T859
Test name
Test status
Simulation time 37483804 ps
CPU time 0.81 seconds
Started Aug 06 04:32:35 PM PDT 24
Finished Aug 06 04:32:36 PM PDT 24
Peak memory 195300 kb
Host smart-6036fb5f-46ba-480e-8d40-2ed1a18add8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=332112020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.332112020
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050769748
Short name T853
Test name
Test status
Simulation time 235432585 ps
CPU time 1.09 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:38 PM PDT 24
Peak memory 196276 kb
Host smart-b75bca7a-66d8-4856-a6df-95545caa1d59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050769748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2050769748
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1477577519
Short name T874
Test name
Test status
Simulation time 17751310 ps
CPU time 0.7 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:37 PM PDT 24
Peak memory 194748 kb
Host smart-5190dfb5-7420-42e5-b73e-81859dce6596
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1477577519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1477577519
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.912488613
Short name T919
Test name
Test status
Simulation time 64883374 ps
CPU time 1.01 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 196328 kb
Host smart-fb1089a9-1368-47f2-898f-5eae3fc342a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912488613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.912488613
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2838351463
Short name T928
Test name
Test status
Simulation time 155990762 ps
CPU time 1.31 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197816 kb
Host smart-78e6449a-f525-48ec-8739-5a0d32fe02e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2838351463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2838351463
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1649279713
Short name T895
Test name
Test status
Simulation time 84976440 ps
CPU time 1.23 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197880 kb
Host smart-b29b74af-969a-4444-9fdc-4cd8fcd2904a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649279713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1649279713
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1655358637
Short name T870
Test name
Test status
Simulation time 66315906 ps
CPU time 1.3 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 196440 kb
Host smart-ce181b0c-1965-4026-825a-ed3db186e98a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1655358637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1655358637
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1287806539
Short name T885
Test name
Test status
Simulation time 63577849 ps
CPU time 1.14 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 196376 kb
Host smart-313e923c-79e8-4819-a559-f9155967689d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287806539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1287806539
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.4178484385
Short name T918
Test name
Test status
Simulation time 70347446 ps
CPU time 0.81 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 195936 kb
Host smart-eaab5852-7996-4534-adf2-2b362f902c15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4178484385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.4178484385
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.739825479
Short name T896
Test name
Test status
Simulation time 26882904 ps
CPU time 0.8 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196008 kb
Host smart-8b3bd7ca-1c4e-4c7a-b6af-623f37f0b8ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739825479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.739825479
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2073788760
Short name T902
Test name
Test status
Simulation time 131333239 ps
CPU time 0.77 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:39 PM PDT 24
Peak memory 195096 kb
Host smart-30131d88-ffa3-46aa-b005-6b948f364b6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2073788760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2073788760
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905456144
Short name T884
Test name
Test status
Simulation time 181581174 ps
CPU time 1.23 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196372 kb
Host smart-c4c4bf5e-6a58-44a3-a420-755f62ebda85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905456144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2905456144
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.273206944
Short name T856
Test name
Test status
Simulation time 18890346 ps
CPU time 0.73 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 195184 kb
Host smart-4d455d7c-abb6-4897-904e-5e940f61af27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=273206944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.273206944
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.899063381
Short name T904
Test name
Test status
Simulation time 199565246 ps
CPU time 1.1 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 196560 kb
Host smart-41815c02-7217-4c1c-82c4-b71381ff5e74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899063381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.899063381
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3510197590
Short name T889
Test name
Test status
Simulation time 71196310 ps
CPU time 1.22 seconds
Started Aug 06 04:32:41 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 195668 kb
Host smart-b8abb623-d668-4100-8151-456f378e5c36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3510197590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3510197590
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.227106771
Short name T894
Test name
Test status
Simulation time 199626400 ps
CPU time 1.46 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196628 kb
Host smart-590a3853-a66a-4b80-97d4-09d4c33329e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227106771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.227106771
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1866446393
Short name T879
Test name
Test status
Simulation time 180749759 ps
CPU time 0.97 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196352 kb
Host smart-4caed501-e584-421d-a11b-84a0680084fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1866446393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1866446393
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2733642728
Short name T922
Test name
Test status
Simulation time 126910850 ps
CPU time 1 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 195500 kb
Host smart-0bdc960d-46e4-4951-b819-aac33b92a9af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733642728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2733642728
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2662064248
Short name T935
Test name
Test status
Simulation time 238911819 ps
CPU time 0.98 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 195472 kb
Host smart-323f79f9-6632-47bb-9afa-1e3499c09583
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2662064248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2662064248
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.65633467
Short name T909
Test name
Test status
Simulation time 44998872 ps
CPU time 1.13 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 197908 kb
Host smart-53adb804-e663-4bd9-bc58-4b8f2f0b7e71
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65633467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.65633467
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1317616370
Short name T890
Test name
Test status
Simulation time 231385260 ps
CPU time 1.13 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 197864 kb
Host smart-1c331ddf-5de7-4ffd-a907-fb347ff906db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1317616370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1317616370
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1711074533
Short name T925
Test name
Test status
Simulation time 377259910 ps
CPU time 1.07 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 196320 kb
Host smart-4883e98a-321e-49bc-a137-db96bbe8d28b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711074533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1711074533
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3801928398
Short name T931
Test name
Test status
Simulation time 402806507 ps
CPU time 1.18 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196628 kb
Host smart-4873686f-03f2-41b6-b339-5d2e3fb3e4d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3801928398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3801928398
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3085279659
Short name T945
Test name
Test status
Simulation time 182252102 ps
CPU time 1.47 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196488 kb
Host smart-035a4b49-6666-482e-8a1d-b0cee0649723
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085279659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3085279659
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1239620481
Short name T929
Test name
Test status
Simulation time 53983214 ps
CPU time 1.03 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 196420 kb
Host smart-74452484-f638-405b-bafb-df21406fdca1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1239620481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1239620481
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855805972
Short name T891
Test name
Test status
Simulation time 57208670 ps
CPU time 1.07 seconds
Started Aug 06 04:32:46 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 196164 kb
Host smart-8c08225d-b0e1-4eee-a2a6-8049c5d0643d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855805972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3855805972
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1671748205
Short name T905
Test name
Test status
Simulation time 54334116 ps
CPU time 1.06 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 196556 kb
Host smart-7ae315fc-858e-493b-8b14-ce7072829a88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1671748205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1671748205
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2369214811
Short name T923
Test name
Test status
Simulation time 161136905 ps
CPU time 1.47 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 196796 kb
Host smart-7f8c6917-3067-48ea-9194-0b1fe05ed2f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369214811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2369214811
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2837919494
Short name T940
Test name
Test status
Simulation time 337742550 ps
CPU time 1.26 seconds
Started Aug 06 04:32:36 PM PDT 24
Finished Aug 06 04:32:38 PM PDT 24
Peak memory 197996 kb
Host smart-996bf196-89aa-4193-844e-43f68efd43b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2837919494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2837919494
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2191863424
Short name T914
Test name
Test status
Simulation time 41967133 ps
CPU time 0.99 seconds
Started Aug 06 04:32:41 PM PDT 24
Finished Aug 06 04:32:42 PM PDT 24
Peak memory 197236 kb
Host smart-de87c771-0b12-4757-88b7-ae7be873287a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191863424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2191863424
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2288088622
Short name T903
Test name
Test status
Simulation time 145858337 ps
CPU time 1.05 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196492 kb
Host smart-0a3585eb-6b52-4ad6-8529-c390b1cb67f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2288088622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2288088622
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3636388559
Short name T932
Test name
Test status
Simulation time 407423329 ps
CPU time 1.43 seconds
Started Aug 06 04:32:46 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 196396 kb
Host smart-cbe06c1d-f254-463d-9d21-6c124447c239
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636388559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3636388559
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1608426723
Short name T877
Test name
Test status
Simulation time 250935688 ps
CPU time 1.16 seconds
Started Aug 06 04:33:01 PM PDT 24
Finished Aug 06 04:33:02 PM PDT 24
Peak memory 195780 kb
Host smart-c569247e-dbdc-4a82-b460-5a8a2358579b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1608426723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1608426723
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3361841410
Short name T917
Test name
Test status
Simulation time 56235461 ps
CPU time 1.19 seconds
Started Aug 06 04:33:02 PM PDT 24
Finished Aug 06 04:33:03 PM PDT 24
Peak memory 195516 kb
Host smart-5816e519-588b-48e2-b145-b5a4e50dc182
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361841410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3361841410
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3963258443
Short name T857
Test name
Test status
Simulation time 361560318 ps
CPU time 1.44 seconds
Started Aug 06 04:33:02 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 196584 kb
Host smart-3939e109-bb38-4360-8f66-d107ab4b01a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3963258443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3963258443
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840438485
Short name T864
Test name
Test status
Simulation time 38188644 ps
CPU time 1.1 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 196280 kb
Host smart-35605818-6835-4337-86f1-e8827586359b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840438485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3840438485
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3876200783
Short name T939
Test name
Test status
Simulation time 109170002 ps
CPU time 1.02 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 195440 kb
Host smart-105058ac-e954-4281-9a49-ae286f9b9ac2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3876200783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3876200783
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049670441
Short name T893
Test name
Test status
Simulation time 162975896 ps
CPU time 0.92 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 195848 kb
Host smart-fbdcb7d5-0ab7-4769-956d-32182eca2d01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049670441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2049670441
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.661602851
Short name T871
Test name
Test status
Simulation time 581802718 ps
CPU time 1.16 seconds
Started Aug 06 04:33:02 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 196568 kb
Host smart-3428958c-38af-4ade-9c78-d94f2e08e8e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=661602851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.661602851
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3724371889
Short name T908
Test name
Test status
Simulation time 142977082 ps
CPU time 1.31 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 196716 kb
Host smart-0a40b5ea-b7ff-4dc7-8d7a-4e4f5666a7f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724371889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3724371889
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1907048386
Short name T943
Test name
Test status
Simulation time 123982186 ps
CPU time 0.92 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 197696 kb
Host smart-9eaf1b8b-44bd-4cef-9bb9-98fd7f261a47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1907048386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1907048386
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.285431424
Short name T907
Test name
Test status
Simulation time 64387941 ps
CPU time 1.22 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 196672 kb
Host smart-1aa6009f-7bc2-4957-80fd-8f41a4150ab3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285431424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.285431424
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.280054079
Short name T867
Test name
Test status
Simulation time 67496269 ps
CPU time 1.33 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 195608 kb
Host smart-62d6ada0-08f8-4c0a-9ebf-3f4e022dfc79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=280054079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.280054079
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4291347172
Short name T924
Test name
Test status
Simulation time 110842099 ps
CPU time 0.93 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 195044 kb
Host smart-549b265e-0729-404c-a536-12a81dffdbb1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291347172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4291347172
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2591524794
Short name T942
Test name
Test status
Simulation time 166565095 ps
CPU time 1.41 seconds
Started Aug 06 04:33:04 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 198252 kb
Host smart-503cf443-b3f1-43a2-ac3b-8b3f4cee3493
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2591524794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2591524794
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1958282369
Short name T880
Test name
Test status
Simulation time 261590555 ps
CPU time 1.33 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 196524 kb
Host smart-02e10dfc-3e57-4f34-b07a-07774c3bb55c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958282369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1958282369
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3917940247
Short name T883
Test name
Test status
Simulation time 309656155 ps
CPU time 0.9 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 196316 kb
Host smart-35ad0c4a-e95e-4472-8a8c-697e8c8b12f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3917940247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3917940247
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181606662
Short name T910
Test name
Test status
Simulation time 194698891 ps
CPU time 1.06 seconds
Started Aug 06 04:33:00 PM PDT 24
Finished Aug 06 04:33:02 PM PDT 24
Peak memory 196392 kb
Host smart-f9fc7876-2d3a-403d-b79a-257c4f3cae0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181606662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3181606662
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4143169230
Short name T927
Test name
Test status
Simulation time 71831405 ps
CPU time 1.37 seconds
Started Aug 06 04:33:09 PM PDT 24
Finished Aug 06 04:33:10 PM PDT 24
Peak memory 196632 kb
Host smart-8b7878a9-3f88-43b2-b7de-8a32abb6b12f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4143169230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4143169230
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.755953578
Short name T865
Test name
Test status
Simulation time 71390220 ps
CPU time 1.38 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 196352 kb
Host smart-5cebe483-2418-497b-94b1-a26bc3b6c688
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755953578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.755953578
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2244822729
Short name T868
Test name
Test status
Simulation time 193196304 ps
CPU time 1.27 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 195552 kb
Host smart-8d42b82a-8c31-4683-a83f-71e1ec2d4ad7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2244822729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2244822729
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3613880165
Short name T900
Test name
Test status
Simulation time 146022951 ps
CPU time 1.43 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196664 kb
Host smart-67fbfb58-082e-4b07-b14d-309b91137d27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613880165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3613880165
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1703056061
Short name T912
Test name
Test status
Simulation time 70068856 ps
CPU time 0.83 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:11 PM PDT 24
Peak memory 195152 kb
Host smart-f249de8d-2ae7-4241-aeb2-dbfaf97376b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1703056061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1703056061
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233472668
Short name T944
Test name
Test status
Simulation time 322046154 ps
CPU time 1.35 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 196260 kb
Host smart-c969b243-7ae9-4703-bc3e-549049f43f00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233472668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.233472668
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1351754202
Short name T849
Test name
Test status
Simulation time 91404058 ps
CPU time 1.48 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 196596 kb
Host smart-1161f1de-7a4e-4730-9116-0daffe2887b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1351754202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1351754202
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1865605918
Short name T930
Test name
Test status
Simulation time 105919657 ps
CPU time 0.85 seconds
Started Aug 06 04:33:03 PM PDT 24
Finished Aug 06 04:33:04 PM PDT 24
Peak memory 196008 kb
Host smart-e9970285-25dc-4916-83dd-75e3aa531d71
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865605918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1865605918
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3573111019
Short name T947
Test name
Test status
Simulation time 76032525 ps
CPU time 0.78 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 195876 kb
Host smart-9a36f4d2-0cca-41e6-aa90-4db28a78395c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3573111019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3573111019
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1489706888
Short name T875
Test name
Test status
Simulation time 770118404 ps
CPU time 1.29 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 196480 kb
Host smart-70dca7de-1858-491c-a9ac-0c6fd80f4855
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489706888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1489706888
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2015195745
Short name T898
Test name
Test status
Simulation time 414855502 ps
CPU time 1.32 seconds
Started Aug 06 04:33:06 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 196520 kb
Host smart-7fffc566-fb65-4783-ae33-61de3fc62428
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2015195745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2015195745
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805646047
Short name T882
Test name
Test status
Simulation time 49881023 ps
CPU time 0.98 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 196420 kb
Host smart-b707441b-4a4c-4e50-a56c-0d75fe13dd51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805646047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.805646047
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1948496717
Short name T899
Test name
Test status
Simulation time 370969986 ps
CPU time 1.43 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 196396 kb
Host smart-158c14c0-4b98-49de-9a3a-cee580637410
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1948496717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1948496717
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1526878341
Short name T855
Test name
Test status
Simulation time 24822939 ps
CPU time 0.74 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 193992 kb
Host smart-b2d0bc79-0c6a-4bb5-ad7c-204d7db17e81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526878341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1526878341
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.206223456
Short name T906
Test name
Test status
Simulation time 277593772 ps
CPU time 1.24 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 196280 kb
Host smart-d955d5dd-f431-456e-b4e4-ec9e8ed5bf76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=206223456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.206223456
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3386044618
Short name T860
Test name
Test status
Simulation time 234619227 ps
CPU time 1.13 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:06 PM PDT 24
Peak memory 195816 kb
Host smart-6efcc315-07c9-47d7-abba-3cd09b636b72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386044618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3386044618
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2071634177
Short name T911
Test name
Test status
Simulation time 275085586 ps
CPU time 1.29 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:09 PM PDT 24
Peak memory 196764 kb
Host smart-af0e343c-c36d-41ed-aee6-f54e6283cea6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2071634177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2071634177
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488726107
Short name T941
Test name
Test status
Simulation time 30572676 ps
CPU time 1.05 seconds
Started Aug 06 04:33:05 PM PDT 24
Finished Aug 06 04:33:07 PM PDT 24
Peak memory 196064 kb
Host smart-1dd25753-54a3-412d-86b9-701e263aaa2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488726107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.488726107
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3710813927
Short name T862
Test name
Test status
Simulation time 469037417 ps
CPU time 1.01 seconds
Started Aug 06 04:33:13 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 197164 kb
Host smart-15edb126-bb31-4494-ace2-8e34d174dc46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3710813927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3710813927
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1774407086
Short name T881
Test name
Test status
Simulation time 68877097 ps
CPU time 1.18 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 195700 kb
Host smart-8be3e6c9-515a-461f-ac6f-49e332c0ad0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774407086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1774407086
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4051645108
Short name T851
Test name
Test status
Simulation time 99037654 ps
CPU time 0.72 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 194988 kb
Host smart-4f2e91bf-7a6a-46b9-bbd0-73917efb4ac0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4051645108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4051645108
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.679228710
Short name T920
Test name
Test status
Simulation time 73274183 ps
CPU time 0.83 seconds
Started Aug 06 04:33:10 PM PDT 24
Finished Aug 06 04:33:11 PM PDT 24
Peak memory 195196 kb
Host smart-0e55ae1e-c905-49fd-bd1a-662617a366d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679228710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.679228710
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.829502405
Short name T873
Test name
Test status
Simulation time 30204791 ps
CPU time 0.99 seconds
Started Aug 06 04:33:12 PM PDT 24
Finished Aug 06 04:33:14 PM PDT 24
Peak memory 196468 kb
Host smart-e9e87f14-bbaf-49e7-bb59-9bd2d105bb82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=829502405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.829502405
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2008197488
Short name T866
Test name
Test status
Simulation time 225927446 ps
CPU time 1.33 seconds
Started Aug 06 04:33:07 PM PDT 24
Finished Aug 06 04:33:08 PM PDT 24
Peak memory 197952 kb
Host smart-c691658e-bb07-48a1-a997-eee21d26604e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008197488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2008197488
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2724674385
Short name T863
Test name
Test status
Simulation time 381199165 ps
CPU time 1.54 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 196608 kb
Host smart-7a81380d-eff5-4514-97bb-dd7bff54a697
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2724674385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2724674385
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371459424
Short name T938
Test name
Test status
Simulation time 750708732 ps
CPU time 1 seconds
Started Aug 06 04:32:40 PM PDT 24
Finished Aug 06 04:32:41 PM PDT 24
Peak memory 197644 kb
Host smart-7c08f6ed-b4d1-4824-a323-affe5c495fc1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371459424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3371459424
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.614532475
Short name T850
Test name
Test status
Simulation time 80778522 ps
CPU time 1.01 seconds
Started Aug 06 04:32:43 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 197964 kb
Host smart-ac5e5280-173d-4501-9436-c86761c8e5a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=614532475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.614532475
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2111508236
Short name T886
Test name
Test status
Simulation time 264940068 ps
CPU time 0.95 seconds
Started Aug 06 04:32:44 PM PDT 24
Finished Aug 06 04:32:45 PM PDT 24
Peak memory 197772 kb
Host smart-ef165052-5085-486a-84b0-4fa1df6f38c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111508236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2111508236
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2106253032
Short name T876
Test name
Test status
Simulation time 281685489 ps
CPU time 1.17 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 195824 kb
Host smart-6474f70e-b315-4b4d-b5c4-0dab758a3024
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2106253032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2106253032
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3384969210
Short name T861
Test name
Test status
Simulation time 54045766 ps
CPU time 1.33 seconds
Started Aug 06 04:32:39 PM PDT 24
Finished Aug 06 04:32:40 PM PDT 24
Peak memory 196192 kb
Host smart-742490fe-f6fe-48bf-a3ae-435fefe1ab20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384969210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3384969210
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1145274275
Short name T854
Test name
Test status
Simulation time 149134171 ps
CPU time 0.85 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:43 PM PDT 24
Peak memory 195920 kb
Host smart-78406104-5e7d-4c3e-899c-660d18613a04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1145274275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1145274275
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054628998
Short name T872
Test name
Test status
Simulation time 148725238 ps
CPU time 1.28 seconds
Started Aug 06 04:32:46 PM PDT 24
Finished Aug 06 04:32:47 PM PDT 24
Peak memory 195836 kb
Host smart-6e4bc086-7a9d-40dd-8cf0-7e1e50ee93a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054628998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4054628998
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1110502778
Short name T887
Test name
Test status
Simulation time 90396833 ps
CPU time 1.05 seconds
Started Aug 06 04:32:45 PM PDT 24
Finished Aug 06 04:32:46 PM PDT 24
Peak memory 195492 kb
Host smart-376181f6-52f3-42ff-a9b9-a8936d7901b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1110502778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1110502778
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.207107837
Short name T916
Test name
Test status
Simulation time 84889593 ps
CPU time 1.43 seconds
Started Aug 06 04:32:42 PM PDT 24
Finished Aug 06 04:32:44 PM PDT 24
Peak memory 196388 kb
Host smart-352ae7e3-6359-46d7-bf1a-ca4dc1e84de8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207107837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.207107837
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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