Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16826606	1			T32	14973		T1	66		T11	99
all_values[1]	16826606	1			T32	14973		T1	66		T11	99
all_values[2]	16826606	1			T32	14973		T1	66		T11	99
all_values[3]	16826606	1			T32	14973		T1	66		T11	99
all_values[4]	16826606	1			T32	14973		T1	66		T11	99
all_values[5]	16826606	1			T32	14973		T1	66		T11	99
all_values[6]	16826606	1			T32	14973		T1	66		T11	99
all_values[7]	16826606	1			T32	14973		T1	66		T11	99
all_values[8]	16826606	1			T32	14973		T1	66		T11	99
all_values[9]	16826606	1			T32	14973		T1	66		T11	99
all_values[10]	16826606	1			T32	14973		T1	66		T11	99
all_values[11]	16826606	1			T32	14973		T1	66		T11	99
all_values[12]	16826606	1			T32	14973		T1	66		T11	99
all_values[13]	16826606	1			T32	14973		T1	66		T11	99
all_values[14]	16826606	1			T32	14973		T1	66		T11	99
all_values[15]	16826606	1			T32	14973		T1	66		T11	99
all_values[16]	16826606	1			T32	14973		T1	66		T11	99
all_values[17]	16826606	1			T32	14973		T1	66		T11	99
all_values[18]	16826606	1			T32	14973		T1	66		T11	99
all_values[19]	16826606	1			T32	14973		T1	66		T11	99
all_values[20]	16826606	1			T32	14973		T1	66		T11	99
all_values[21]	16826606	1			T32	14973		T1	66		T11	99
all_values[22]	16826606	1			T32	14973		T1	66		T11	99
all_values[23]	16826606	1			T32	14973		T1	66		T11	99
all_values[24]	16826606	1			T32	14973		T1	66		T11	99
all_values[25]	16826606	1			T32	14973		T1	66		T11	99
all_values[26]	16826606	1			T32	14973		T1	66		T11	99
all_values[27]	16826606	1			T32	14973		T1	66		T11	99
all_values[28]	16826606	1			T32	14973		T1	66		T11	99
all_values[29]	16826606	1			T32	14973		T1	66		T11	99
all_values[30]	16826606	1			T32	14973		T1	66		T11	99
all_values[31]	16826606	1			T32	14973		T1	66		T11	99

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301750336

1

T32

258298

T1

1638

T11

2159

auto[1]

236701056

1

T32

220838

T1

474

T11

1009

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110946890

1

T32

80595

T1

1411

T11

2167

auto[1]

427504502

1

T32

398541

T1

701

T11

1001

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2746242	1			T32	1784		T1	44		T11	38
all_values[0]	auto[0]	auto[1]	6700354	1			T32	6275		T1	7		T11	22
all_values[0]	auto[1]	auto[0]	716904	1			T32	760		T1	4		T11	25
all_values[0]	auto[1]	auto[1]	6663106	1			T32	6154		T1	11		T11	14
all_values[1]	auto[0]	auto[0]	2743094	1			T32	1871		T1	43		T11	38
all_values[1]	auto[0]	auto[1]	6647002	1			T32	6519		T1	23		T11	21
all_values[1]	auto[1]	auto[0]	720877	1			T32	502		T11	24		T13	19366
all_values[1]	auto[1]	auto[1]	6715633	1			T32	6081		T11	16		T13	183678
all_values[2]	auto[0]	auto[0]	2752654	1			T32	1674		T1	48		T11	41
all_values[2]	auto[0]	auto[1]	6692412	1			T32	5964		T1	12		T11	17
all_values[2]	auto[1]	auto[0]	723906	1			T32	547		T1	6		T11	23
all_values[2]	auto[1]	auto[1]	6657634	1			T32	6788		T11	18		T13	180131
all_values[3]	auto[0]	auto[0]	2749166	1			T32	1670		T1	55		T11	64
all_values[3]	auto[0]	auto[1]	6659919	1			T32	5541		T1	11		T11	18
all_values[3]	auto[1]	auto[0]	722784	1			T32	634		T11	13		T13	18025
all_values[3]	auto[1]	auto[1]	6694737	1			T32	7128		T11	4		T13	185594
all_values[4]	auto[0]	auto[0]	2749462	1			T32	1653		T1	39		T11	55
all_values[4]	auto[0]	auto[1]	6725348	1			T32	6599		T1	16		T11	29
all_values[4]	auto[1]	auto[0]	719652	1			T32	622		T1	4		T11	9
all_values[4]	auto[1]	auto[1]	6632144	1			T32	6099		T1	7		T11	6
all_values[5]	auto[0]	auto[0]	2756944	1			T32	1771		T1	36		T11	56
all_values[5]	auto[0]	auto[1]	6685950	1			T32	6016		T1	15		T11	9
all_values[5]	auto[1]	auto[0]	712382	1			T32	657		T1	3		T11	23
all_values[5]	auto[1]	auto[1]	6671330	1			T32	6529		T1	12		T11	11
all_values[6]	auto[0]	auto[0]	2754030	1			T32	1668		T1	34		T11	49
all_values[6]	auto[0]	auto[1]	6665437	1			T32	7320		T1	15		T11	17
all_values[6]	auto[1]	auto[0]	723348	1			T32	507		T1	5		T11	19
all_values[6]	auto[1]	auto[1]	6683791	1			T32	5478		T1	12		T11	14
all_values[7]	auto[0]	auto[0]	2746149	1			T32	2316		T1	39		T11	65
all_values[7]	auto[0]	auto[1]	6686370	1			T32	5576		T1	7		T11	17
all_values[7]	auto[1]	auto[0]	708416	1			T32	736		T1	5		T11	11
all_values[7]	auto[1]	auto[1]	6685671	1			T32	6345		T1	15		T11	6
all_values[8]	auto[0]	auto[0]	2750339	1			T32	1858		T1	39		T11	42
all_values[8]	auto[0]	auto[1]	6672487	1			T32	5307		T1	12		T11	17
all_values[8]	auto[1]	auto[0]	719601	1			T32	507		T1	6		T11	23
all_values[8]	auto[1]	auto[1]	6684179	1			T32	7301		T1	9		T11	17
all_values[9]	auto[0]	auto[0]	2744600	1			T32	1771		T1	27		T11	60
all_values[9]	auto[0]	auto[1]	6693811	1			T32	5719		T1	22		T11	13
all_values[9]	auto[1]	auto[0]	718643	1			T32	544		T1	8		T11	18
all_values[9]	auto[1]	auto[1]	6669552	1			T32	6939		T1	9		T11	8
all_values[10]	auto[0]	auto[0]	2756527	1			T32	1777		T1	41		T11	37
all_values[10]	auto[0]	auto[1]	6662691	1			T32	7267		T1	19		T11	32
all_values[10]	auto[1]	auto[0]	728923	1			T32	638		T1	5		T11	27
all_values[10]	auto[1]	auto[1]	6678465	1			T32	5291		T1	1		T11	3
all_values[11]	auto[0]	auto[0]	2754056	1			T32	1745		T1	31		T11	46
all_values[11]	auto[0]	auto[1]	6661989	1			T32	7443		T1	29		T11	7
all_values[11]	auto[1]	auto[0]	717306	1			T32	719		T1	6		T11	19
all_values[11]	auto[1]	auto[1]	6693255	1			T32	5066		T11	27		T13	179638
all_values[12]	auto[0]	auto[0]	2748912	1			T32	1781		T1	47		T11	37
all_values[12]	auto[0]	auto[1]	6677354	1			T32	6351		T1	13		T11	16
all_values[12]	auto[1]	auto[0]	715121	1			T32	705		T1	6		T11	38
all_values[12]	auto[1]	auto[1]	6685219	1			T32	6136		T11	8		T13	178265
all_values[13]	auto[0]	auto[0]	2746271	1			T32	1865		T1	45		T11	37
all_values[13]	auto[0]	auto[1]	6675811	1			T32	6474		T1	15		T11	17
all_values[13]	auto[1]	auto[0]	715912	1			T32	541		T1	5		T11	26
all_values[13]	auto[1]	auto[1]	6688612	1			T32	6093		T1	1		T11	19
all_values[14]	auto[0]	auto[0]	2746172	1			T32	1717		T1	26		T11	60
all_values[14]	auto[0]	auto[1]	6666107	1			T32	6315		T1	14		T11	28
all_values[14]	auto[1]	auto[0]	724280	1			T32	418		T1	4		T11	8
all_values[14]	auto[1]	auto[1]	6690047	1			T32	6523		T1	22		T11	3
all_values[15]	auto[0]	auto[0]	2748172	1			T32	2626		T1	29		T11	45
all_values[15]	auto[0]	auto[1]	6669245	1			T32	5239		T1	11		T11	27
all_values[15]	auto[1]	auto[0]	729204	1			T32	617		T1	12		T11	20
all_values[15]	auto[1]	auto[1]	6679985	1			T32	6491		T1	14		T11	7
all_values[16]	auto[0]	auto[0]	2747255	1			T32	1866		T1	29		T11	47
all_values[16]	auto[0]	auto[1]	6684790	1			T32	5392		T1	11		T11	11
all_values[16]	auto[1]	auto[0]	714350	1			T32	1671		T1	10		T11	31
all_values[16]	auto[1]	auto[1]	6680211	1			T32	6044		T1	16		T11	10
all_values[17]	auto[0]	auto[0]	2742882	1			T32	1703		T1	44		T11	41
all_values[17]	auto[0]	auto[1]	6700344	1			T32	6458		T1	5		T11	24
all_values[17]	auto[1]	auto[0]	710891	1			T32	546		T1	14		T11	28
all_values[17]	auto[1]	auto[1]	6672489	1			T32	6266		T1	3		T11	6
all_values[18]	auto[0]	auto[0]	2741083	1			T32	1666		T1	37		T11	49
all_values[18]	auto[0]	auto[1]	6712408	1			T32	7203		T1	3		T11	3
all_values[18]	auto[1]	auto[0]	719499	1			T32	674		T1	18		T11	34
all_values[18]	auto[1]	auto[1]	6653616	1			T32	5430		T1	8		T11	13
all_values[19]	auto[0]	auto[0]	2756580	1			T32	1699		T1	39		T11	37
all_values[19]	auto[0]	auto[1]	6673166	1			T32	6011		T1	12		T11	21
all_values[19]	auto[1]	auto[0]	713759	1			T32	536		T1	7		T11	29
all_values[19]	auto[1]	auto[1]	6683101	1			T32	6727		T1	8		T11	12
all_values[20]	auto[0]	auto[0]	2745022	1			T32	1780		T1	31		T11	53
all_values[20]	auto[0]	auto[1]	6657199	1			T32	6057		T1	15		T11	24
all_values[20]	auto[1]	auto[0]	721922	1			T32	511		T1	4		T11	10
all_values[20]	auto[1]	auto[1]	6702463	1			T32	6625		T1	16		T11	12
all_values[21]	auto[0]	auto[0]	2743797	1			T32	1709		T1	36		T11	45
all_values[21]	auto[0]	auto[1]	6660767	1			T32	6473		T1	30		T11	17
all_values[21]	auto[1]	auto[0]	706174	1			T32	564		T11	21		T13	18039
all_values[21]	auto[1]	auto[1]	6715868	1			T32	6227		T11	16		T13	183156
all_values[22]	auto[0]	auto[0]	2756544	1			T32	2927		T1	31		T11	60
all_values[22]	auto[0]	auto[1]	6674033	1			T32	4690		T1	18		T11	18
all_values[22]	auto[1]	auto[0]	714889	1			T32	737		T1	8		T11	14
all_values[22]	auto[1]	auto[1]	6681140	1			T32	6619		T1	9		T11	7
all_values[23]	auto[0]	auto[0]	2738637	1			T32	1724		T1	31		T11	46
all_values[23]	auto[0]	auto[1]	6692901	1			T32	6776		T1	24		T11	14
all_values[23]	auto[1]	auto[0]	725774	1			T32	397		T1	11		T11	18
all_values[23]	auto[1]	auto[1]	6669294	1			T32	6076		T11	21		T13	179209
all_values[24]	auto[0]	auto[0]	2745421	1			T32	1825		T1	33		T11	40
all_values[24]	auto[0]	auto[1]	6707448	1			T32	7435		T1	13		T11	33
all_values[24]	auto[1]	auto[0]	723655	1			T32	570		T1	12		T11	22
all_values[24]	auto[1]	auto[1]	6650082	1			T32	5143		T1	8		T11	4
all_values[25]	auto[0]	auto[0]	2752391	1			T32	1846		T1	47		T11	42
all_values[25]	auto[0]	auto[1]	6700297	1			T32	7261		T1	10		T11	25
all_values[25]	auto[1]	auto[0]	710254	1			T32	592		T1	7		T11	12
all_values[25]	auto[1]	auto[1]	6663664	1			T32	5274		T1	2		T11	20
all_values[26]	auto[0]	auto[0]	2753482	1			T32	1854		T1	37		T11	44
all_values[26]	auto[0]	auto[1]	6675151	1			T32	5126		T1	3		T11	21
all_values[26]	auto[1]	auto[0]	721278	1			T32	1619		T1	8		T11	26
all_values[26]	auto[1]	auto[1]	6676695	1			T32	6374		T1	18		T11	8
all_values[27]	auto[0]	auto[0]	2749074	1			T32	1760		T1	30		T11	66
all_values[27]	auto[0]	auto[1]	6708159	1			T32	5082		T1	19		T11	11
all_values[27]	auto[1]	auto[0]	725610	1			T32	640		T1	9		T11	14
all_values[27]	auto[1]	auto[1]	6643763	1			T32	7491		T1	8		T11	8
all_values[28]	auto[0]	auto[0]	2746162	1			T32	1715		T1	36		T11	41
all_values[28]	auto[0]	auto[1]	6652657	1			T32	6906		T1	10		T11	37
all_values[28]	auto[1]	auto[0]	722295	1			T32	633		T1	11		T11	9
all_values[28]	auto[1]	auto[1]	6705492	1			T32	5719		T1	9		T11	12
all_values[29]	auto[0]	auto[0]	2743481	1			T32	1827		T1	34		T11	36
all_values[29]	auto[0]	auto[1]	6690767	1			T32	7778		T1	6		T11	18
all_values[29]	auto[1]	auto[0]	718812	1			T32	502		T1	17		T11	25
all_values[29]	auto[1]	auto[1]	6673546	1			T32	4866		T1	9		T11	20
all_values[30]	auto[0]	auto[0]	2742560	1			T32	1818		T1	34		T11	61
all_values[30]	auto[0]	auto[1]	6666257	1			T32	4931		T1	6		T11	28
all_values[30]	auto[1]	auto[0]	725680	1			T32	583		T1	12		T11	7
all_values[30]	auto[1]	auto[1]	6692109	1			T32	7641		T1	14		T11	3
all_values[31]	auto[0]	auto[0]	2746479	1			T32	2323		T1	27		T11	38
all_values[31]	auto[0]	auto[1]	6708065	1			T32	5205		T1	33		T11	31
all_values[31]	auto[1]	auto[0]	711149	1			T32	577		T1	5		T11	25
all_values[31]	auto[1]	auto[1]	6660913	1			T32	6868		T1	1		T11	5