Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5246505	1			T32	4180		T1	37		T11	55
all_pins[1]	5246505	1			T32	4180		T1	37		T11	55
all_pins[2]	5246505	1			T32	4180		T1	37		T11	55
all_pins[3]	5246505	1			T32	4180		T1	37		T11	55
all_pins[4]	5246505	1			T32	4180		T1	37		T11	55
all_pins[5]	5246505	1			T32	4180		T1	37		T11	55
all_pins[6]	5246505	1			T32	4180		T1	37		T11	55
all_pins[7]	5246505	1			T32	4180		T1	37		T11	55
all_pins[8]	5246505	1			T32	4180		T1	37		T11	55
all_pins[9]	5246505	1			T32	4180		T1	37		T11	55
all_pins[10]	5246505	1			T32	4180		T1	37		T11	55
all_pins[11]	5246505	1			T32	4180		T1	37		T11	55
all_pins[12]	5246505	1			T32	4180		T1	37		T11	55
all_pins[13]	5246505	1			T32	4180		T1	37		T11	55
all_pins[14]	5246505	1			T32	4180		T1	37		T11	55
all_pins[15]	5246505	1			T32	4180		T1	37		T11	55
all_pins[16]	5246505	1			T32	4180		T1	37		T11	55
all_pins[17]	5246505	1			T32	4180		T1	37		T11	55
all_pins[18]	5246505	1			T32	4180		T1	37		T11	55
all_pins[19]	5246505	1			T32	4180		T1	37		T11	55
all_pins[20]	5246505	1			T32	4180		T1	37		T11	55
all_pins[21]	5246505	1			T32	4180		T1	37		T11	55
all_pins[22]	5246505	1			T32	4180		T1	37		T11	55
all_pins[23]	5246505	1			T32	4180		T1	37		T11	55
all_pins[24]	5246505	1			T32	4180		T1	37		T11	55
all_pins[25]	5246505	1			T32	4180		T1	37		T11	55
all_pins[26]	5246505	1			T32	4180		T1	37		T11	55
all_pins[27]	5246505	1			T32	4180		T1	37		T11	55
all_pins[28]	5246505	1			T32	4180		T1	37		T11	55
all_pins[29]	5246505	1			T32	4180		T1	37		T11	55
all_pins[30]	5246505	1			T32	4180		T1	37		T11	55
all_pins[31]	5246505	1			T32	4180		T1	37		T11	55

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	104302265	1			T32	83885		T1	998		T11	1454
values[0x1]	63585895	1			T32	49875		T1	186		T11	306
transitions[0x0=>0x1]	38119807	1			T32	30369		T1	124		T11	226
transitions[0x1=>0x0]	38119648	1			T32	30369		T1	124		T11	226

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3262602	1			T32	2607		T1	27		T11	43
all_pins[0]	values[0x1]	1983903	1			T32	1573		T1	10		T11	12
all_pins[0]	transitions[0x0=>0x1]	1226899	1			T32	969		T1	10		T11	11
all_pins[0]	transitions[0x1=>0x0]	1232509	1			T32	968		T1	1		T11	4
all_pins[1]	values[0x0]	3254950	1			T32	2630		T1	37		T11	40
all_pins[1]	values[0x1]	1991555	1			T32	1550		T11	15		T13	53432
all_pins[1]	transitions[0x0=>0x1]	1193800	1			T32	901		T11	10		T13	32964
all_pins[1]	transitions[0x1=>0x0]	1186148	1			T32	924		T1	10		T11	7
all_pins[2]	values[0x0]	3257332	1			T32	2509		T1	37		T11	40
all_pins[2]	values[0x1]	1989173	1			T32	1671		T11	15		T13	53226
all_pins[2]	transitions[0x0=>0x1]	1189909	1			T32	1058		T11	8		T13	31578
all_pins[2]	transitions[0x1=>0x0]	1192291	1			T32	937		T11	8		T13	31784
all_pins[3]	values[0x0]	3257447	1			T32	2482		T1	37		T11	51
all_pins[3]	values[0x1]	1989058	1			T32	1698		T11	4		T13	52727
all_pins[3]	transitions[0x0=>0x1]	1190448	1			T32	1003		T11	1		T13	31162
all_pins[3]	transitions[0x1=>0x0]	1190563	1			T32	976		T11	12		T13	31661
all_pins[4]	values[0x0]	3263808	1			T32	2721		T1	33		T11	49
all_pins[4]	values[0x1]	1982697	1			T32	1459		T1	4		T11	6
all_pins[4]	transitions[0x0=>0x1]	1186877	1			T32	815		T1	4		T11	2
all_pins[4]	transitions[0x1=>0x0]	1193238	1			T32	1054		T13	31946		T16	5
all_pins[5]	values[0x0]	3263662	1			T32	2690		T1	27		T11	46
all_pins[5]	values[0x1]	1982843	1			T32	1490		T1	10		T11	9
all_pins[5]	transitions[0x0=>0x1]	1189052	1			T32	911		T1	10		T11	8
all_pins[5]	transitions[0x1=>0x0]	1188906	1			T32	880		T1	4		T11	5
all_pins[6]	values[0x0]	3258060	1			T32	2582		T1	27		T11	40
all_pins[6]	values[0x1]	1988445	1			T32	1598		T1	10		T11	15
all_pins[6]	transitions[0x0=>0x1]	1195231	1			T32	1067		T1	7		T11	11
all_pins[6]	transitions[0x1=>0x0]	1189629	1			T32	959		T1	7		T11	5
all_pins[7]	values[0x0]	3262519	1			T32	2515		T1	27		T11	49
all_pins[7]	values[0x1]	1983986	1			T32	1665		T1	10		T11	6
all_pins[7]	transitions[0x0=>0x1]	1187541	1			T32	1033		T1	6		T11	3
all_pins[7]	transitions[0x1=>0x0]	1192000	1			T32	966		T1	6		T11	12
all_pins[8]	values[0x0]	3261808	1			T32	2619		T1	30		T11	42
all_pins[8]	values[0x1]	1984697	1			T32	1561		T1	7		T11	13
all_pins[8]	transitions[0x0=>0x1]	1187547	1			T32	896		T1	1		T11	9
all_pins[8]	transitions[0x1=>0x0]	1186836	1			T32	1000		T1	4		T11	2
all_pins[9]	values[0x0]	3257333	1			T32	2546		T1	30		T11	46
all_pins[9]	values[0x1]	1989172	1			T32	1634		T1	7		T11	9
all_pins[9]	transitions[0x0=>0x1]	1192551	1			T32	1053		T1	7		T11	5
all_pins[9]	transitions[0x1=>0x0]	1188076	1			T32	980		T1	7		T11	9
all_pins[10]	values[0x0]	3261394	1			T32	2565		T1	36		T11	53
all_pins[10]	values[0x1]	1985111	1			T32	1615		T1	1		T11	2
all_pins[10]	transitions[0x0=>0x1]	1187292	1			T32	931		T1	1		T11	2
all_pins[10]	transitions[0x1=>0x0]	1191353	1			T32	950		T1	7		T11	9
all_pins[11]	values[0x0]	3255046	1			T32	2728		T1	37		T11	34
all_pins[11]	values[0x1]	1991459	1			T32	1452		T11	21		T13	52069
all_pins[11]	transitions[0x0=>0x1]	1193901	1			T32	859		T11	19		T13	30803
all_pins[11]	transitions[0x1=>0x0]	1187553	1			T32	1022		T1	1		T13	31270
all_pins[12]	values[0x0]	3259658	1			T32	2641		T1	37		T11	48
all_pins[12]	values[0x1]	1986847	1			T32	1539		T11	7		T13	51956
all_pins[12]	transitions[0x0=>0x1]	1189037	1			T32	1003		T11	5		T13	31572
all_pins[12]	transitions[0x1=>0x0]	1193649	1			T32	916		T11	19		T13	31685
all_pins[13]	values[0x0]	3258128	1			T32	2604		T1	36		T11	36
all_pins[13]	values[0x1]	1988377	1			T32	1576		T1	1		T11	19
all_pins[13]	transitions[0x0=>0x1]	1190581	1			T32	1044		T1	1		T11	16
all_pins[13]	transitions[0x1=>0x0]	1189051	1			T32	1007		T11	4		T13	30997
all_pins[14]	values[0x0]	3256191	1			T32	2579		T1	19		T11	52
all_pins[14]	values[0x1]	1990314	1			T32	1601		T1	18		T11	3
all_pins[14]	transitions[0x0=>0x1]	1193102	1			T32	945		T1	17		T11	2
all_pins[14]	transitions[0x1=>0x0]	1191165	1			T32	920		T11	18		T13	31873
all_pins[15]	values[0x0]	3257863	1			T32	2569		T1	28		T11	50
all_pins[15]	values[0x1]	1988642	1			T32	1611		T1	9		T11	5
all_pins[15]	transitions[0x0=>0x1]	1188586	1			T32	916		T1	1		T11	5
all_pins[15]	transitions[0x1=>0x0]	1190258	1			T32	906		T1	10		T11	3
all_pins[16]	values[0x0]	3260993	1			T32	2747		T1	27		T11	45
all_pins[16]	values[0x1]	1985512	1			T32	1433		T1	10		T11	10
all_pins[16]	transitions[0x0=>0x1]	1187644	1			T32	817		T1	2		T11	10
all_pins[16]	transitions[0x1=>0x0]	1190774	1			T32	995		T1	1		T11	5
all_pins[17]	values[0x0]	3261906	1			T32	2616		T1	33		T11	52
all_pins[17]	values[0x1]	1984599	1			T32	1564		T1	4		T11	3
all_pins[17]	transitions[0x0=>0x1]	1190494	1			T32	972		T1	4		T11	3
all_pins[17]	transitions[0x1=>0x0]	1191407	1			T32	841		T1	10		T11	10
all_pins[18]	values[0x0]	3258198	1			T32	2560		T1	29		T11	44
all_pins[18]	values[0x1]	1988307	1			T32	1620		T1	8		T11	11
all_pins[18]	transitions[0x0=>0x1]	1192267	1			T32	1026		T1	8		T11	10
all_pins[18]	transitions[0x1=>0x0]	1188559	1			T32	970		T1	4		T11	2
all_pins[19]	values[0x0]	3262324	1			T32	2448		T1	32		T11	45
all_pins[19]	values[0x1]	1984181	1			T32	1732		T1	5		T11	10
all_pins[19]	transitions[0x0=>0x1]	1186404	1			T32	955		T1	3		T11	5
all_pins[19]	transitions[0x1=>0x0]	1190530	1			T32	843		T1	6		T11	6
all_pins[20]	values[0x0]	3257844	1			T32	2633		T1	27		T11	44
all_pins[20]	values[0x1]	1988661	1			T32	1547		T1	10		T11	11
all_pins[20]	transitions[0x0=>0x1]	1191990	1			T32	969		T1	5		T11	9
all_pins[20]	transitions[0x1=>0x0]	1187510	1			T32	1154		T11	8		T13	31221
all_pins[21]	values[0x0]	3256914	1			T32	2643		T1	37		T11	44
all_pins[21]	values[0x1]	1989591	1			T32	1537		T11	11		T13	53284
all_pins[21]	transitions[0x0=>0x1]	1190184	1			T32	944		T11	3		T13	31849
all_pins[21]	transitions[0x1=>0x0]	1189254	1			T32	954		T1	10		T11	3
all_pins[22]	values[0x0]	3258111	1			T32	2583		T1	30		T11	51
all_pins[22]	values[0x1]	1988394	1			T32	1597		T1	7		T11	4
all_pins[22]	transitions[0x0=>0x1]	1187554	1			T32	923		T1	7		T13	31588
all_pins[22]	transitions[0x1=>0x0]	1188751	1			T32	863		T11	7		T13	31765
all_pins[23]	values[0x0]	3264963	1			T32	2765		T1	37		T11	37
all_pins[23]	values[0x1]	1981542	1			T32	1415		T11	18		T13	53349
all_pins[23]	transitions[0x0=>0x1]	1185453	1			T32	819		T11	14		T13	31806
all_pins[23]	transitions[0x1=>0x0]	1192305	1			T32	1001		T1	7		T13	31564
all_pins[24]	values[0x0]	3257479	1			T32	2661		T1	31		T11	51
all_pins[24]	values[0x1]	1989026	1			T32	1519		T1	6		T11	4
all_pins[24]	transitions[0x0=>0x1]	1192296	1			T32	925		T1	6		T11	3
all_pins[24]	transitions[0x1=>0x0]	1184812	1			T32	821		T11	17		T13	32157
all_pins[25]	values[0x0]	3259219	1			T32	2707		T1	34		T11	40
all_pins[25]	values[0x1]	1987286	1			T32	1473		T1	3		T11	15
all_pins[25]	transitions[0x0=>0x1]	1189379	1			T32	964		T11	15		T13	32117
all_pins[25]	transitions[0x1=>0x0]	1191119	1			T32	1010		T1	3		T11	4
all_pins[26]	values[0x0]	3260247	1			T32	2653		T1	24		T11	48
all_pins[26]	values[0x1]	1986258	1			T32	1527		T1	13		T11	7
all_pins[26]	transitions[0x0=>0x1]	1190806	1			T32	952		T1	10		T11	7
all_pins[26]	transitions[0x1=>0x0]	1191834	1			T32	898		T11	15		T13	32130
all_pins[27]	values[0x0]	3258296	1			T32	2750		T1	32		T11	47
all_pins[27]	values[0x1]	1988209	1			T32	1430		T1	5		T11	8
all_pins[27]	transitions[0x0=>0x1]	1190834	1			T32	923		T11	4		T13	31250
all_pins[27]	transitions[0x1=>0x0]	1188883	1			T32	1020		T1	8		T11	3
all_pins[28]	values[0x0]	3260959	1			T32	2650		T1	30		T11	47
all_pins[28]	values[0x1]	1985546	1			T32	1530		T1	7		T11	8
all_pins[28]	transitions[0x0=>0x1]	1190627	1			T32	964		T1	5		T11	8
all_pins[28]	transitions[0x1=>0x0]	1193290	1			T32	864		T1	3		T11	8
all_pins[29]	values[0x0]	3260001	1			T32	2598		T1	30		T11	38
all_pins[29]	values[0x1]	1986504	1			T32	1582		T1	7		T11	17
all_pins[29]	transitions[0x0=>0x1]	1189727	1			T32	958		T1	3		T11	10
all_pins[29]	transitions[0x1=>0x0]	1188769	1			T32	906		T1	3		T11	1
all_pins[30]	values[0x0]	3260177	1			T32	2676		T1	24		T11	52
all_pins[30]	values[0x1]	1986328	1			T32	1504		T1	13		T11	3
all_pins[30]	transitions[0x0=>0x1]	1188963	1			T32	865		T1	6		T11	3
all_pins[30]	transitions[0x1=>0x0]	1189139	1			T32	943		T11	17		T13	30655
all_pins[31]	values[0x0]	3256833	1			T32	2608		T1	36		T11	50
all_pins[31]	values[0x1]	1989672	1			T32	1572		T1	1		T11	5
all_pins[31]	transitions[0x0=>0x1]	1192831	1			T32	989		T11	5		T13	31194
all_pins[31]	transitions[0x1=>0x0]	1189487	1			T32	921		T1	12		T11	3