Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16826606	1			T32	14973		T1	66		T11	99
all_values[1]	16826606	1			T32	14973		T1	66		T11	99
all_values[2]	16826606	1			T32	14973		T1	66		T11	99
all_values[3]	16826606	1			T32	14973		T1	66		T11	99
all_values[4]	16826606	1			T32	14973		T1	66		T11	99
all_values[5]	16826606	1			T32	14973		T1	66		T11	99
all_values[6]	16826606	1			T32	14973		T1	66		T11	99
all_values[7]	16826606	1			T32	14973		T1	66		T11	99
all_values[8]	16826606	1			T32	14973		T1	66		T11	99
all_values[9]	16826606	1			T32	14973		T1	66		T11	99
all_values[10]	16826606	1			T32	14973		T1	66		T11	99
all_values[11]	16826606	1			T32	14973		T1	66		T11	99
all_values[12]	16826606	1			T32	14973		T1	66		T11	99
all_values[13]	16826606	1			T32	14973		T1	66		T11	99
all_values[14]	16826606	1			T32	14973		T1	66		T11	99
all_values[15]	16826606	1			T32	14973		T1	66		T11	99
all_values[16]	16826606	1			T32	14973		T1	66		T11	99
all_values[17]	16826606	1			T32	14973		T1	66		T11	99
all_values[18]	16826606	1			T32	14973		T1	66		T11	99
all_values[19]	16826606	1			T32	14973		T1	66		T11	99
all_values[20]	16826606	1			T32	14973		T1	66		T11	99
all_values[21]	16826606	1			T32	14973		T1	66		T11	99
all_values[22]	16826606	1			T32	14973		T1	66		T11	99
all_values[23]	16826606	1			T32	14973		T1	66		T11	99
all_values[24]	16826606	1			T32	14973		T1	66		T11	99
all_values[25]	16826606	1			T32	14973		T1	66		T11	99
all_values[26]	16826606	1			T32	14973		T1	66		T11	99
all_values[27]	16826606	1			T32	14973		T1	66		T11	99
all_values[28]	16826606	1			T32	14973		T1	66		T11	99
all_values[29]	16826606	1			T32	14973		T1	66		T11	99
all_values[30]	16826606	1			T32	14973		T1	66		T11	99
all_values[31]	16826606	1			T32	14973		T1	66		T11	99

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301750336

1

T32

258298

T1

1638

T11

2159

auto[1]

236701056

1

T32

220838

T1

474

T11

1009

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110946890

1

T32

80595

T1

1411

T11

2167

auto[1]

427504502

1

T32

398541

T1

701

T11

1001

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

532227446

1

T32

471091

T1

1988

T11

2958

auto[1]

6223946

1

T32

8045

T1

124

T11

210

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2746242	1			T32	1784		T1	44		T11	38
all_values[0]	auto[0]	auto[0]	auto[1]	6602799	1			T32	6149		T1	4		T11	16
all_values[0]	auto[0]	auto[1]	auto[0]	716904	1			T32	760		T1	4		T11	25
all_values[0]	auto[0]	auto[1]	auto[1]	6566081	1			T32	6024		T1	10		T11	11
all_values[0]	auto[1]	auto[0]	auto[1]	97555	1			T32	126		T1	3		T11	6
all_values[0]	auto[1]	auto[1]	auto[1]	97025	1			T32	130		T1	1		T11	3
all_values[1]	auto[0]	auto[0]	auto[0]	2743094	1			T32	1871		T1	43		T11	38
all_values[1]	auto[0]	auto[0]	auto[1]	6549402	1			T32	6388		T1	17		T11	17
all_values[1]	auto[0]	auto[1]	auto[0]	720877	1			T32	502		T11	24		T13	19366
all_values[1]	auto[0]	auto[1]	auto[1]	6618517	1			T32	5955		T11	14		T13	180965
all_values[1]	auto[1]	auto[0]	auto[1]	97600	1			T32	131		T1	6		T11	4
all_values[1]	auto[1]	auto[1]	auto[1]	97116	1			T32	126		T11	2		T13	2713
all_values[2]	auto[0]	auto[0]	auto[0]	2752654	1			T32	1674		T1	48		T11	41
all_values[2]	auto[0]	auto[0]	auto[1]	6594655	1			T32	5844		T1	9		T11	14
all_values[2]	auto[0]	auto[1]	auto[0]	723906	1			T32	547		T1	6		T11	23
all_values[2]	auto[0]	auto[1]	auto[1]	6561007	1			T32	6653		T11	16		T13	177476
all_values[2]	auto[1]	auto[0]	auto[1]	97757	1			T32	120		T1	3		T11	3
all_values[2]	auto[1]	auto[1]	auto[1]	96627	1			T32	135		T11	2		T13	2655
all_values[3]	auto[0]	auto[0]	auto[0]	2749166	1			T32	1670		T1	55		T11	64
all_values[3]	auto[0]	auto[0]	auto[1]	6562524	1			T32	5412		T1	7		T11	15
all_values[3]	auto[0]	auto[1]	auto[0]	722784	1			T32	634		T11	13		T13	18025
all_values[3]	auto[0]	auto[1]	auto[1]	6597684	1			T32	6988		T11	3		T13	182880
all_values[3]	auto[1]	auto[0]	auto[1]	97395	1			T32	129		T1	4		T11	3
all_values[3]	auto[1]	auto[1]	auto[1]	97053	1			T32	140		T11	1		T13	2714
all_values[4]	auto[0]	auto[0]	auto[0]	2749462	1			T32	1653		T1	39		T11	55
all_values[4]	auto[0]	auto[0]	auto[1]	6628218	1			T32	6459		T1	15		T11	23
all_values[4]	auto[0]	auto[1]	auto[0]	719652	1			T32	622		T1	4		T11	9
all_values[4]	auto[0]	auto[1]	auto[1]	6534995	1			T32	5981		T1	5		T11	6
all_values[4]	auto[1]	auto[0]	auto[1]	97130	1			T32	140		T1	1		T11	6
all_values[4]	auto[1]	auto[1]	auto[1]	97149	1			T32	118		T1	2		T13	2801
all_values[5]	auto[0]	auto[0]	auto[0]	2756944	1			T32	1771		T1	36		T11	56
all_values[5]	auto[0]	auto[0]	auto[1]	6588213	1			T32	5887		T1	12		T11	4
all_values[5]	auto[0]	auto[1]	auto[0]	712382	1			T32	657		T1	3		T11	23
all_values[5]	auto[0]	auto[1]	auto[1]	6574620	1			T32	6401		T1	10		T11	9
all_values[5]	auto[1]	auto[0]	auto[1]	97737	1			T32	129		T1	3		T11	5
all_values[5]	auto[1]	auto[1]	auto[1]	96710	1			T32	128		T1	2		T11	2
all_values[6]	auto[0]	auto[0]	auto[0]	2754030	1			T32	1668		T1	34		T11	49
all_values[6]	auto[0]	auto[0]	auto[1]	6568166	1			T32	7204		T1	12		T11	14
all_values[6]	auto[0]	auto[1]	auto[0]	723348	1			T32	507		T1	5		T11	19
all_values[6]	auto[0]	auto[1]	auto[1]	6586625	1			T32	5353		T1	11		T11	13
all_values[6]	auto[1]	auto[0]	auto[1]	97271	1			T32	116		T1	3		T11	3
all_values[6]	auto[1]	auto[1]	auto[1]	97166	1			T32	125		T1	1		T11	1
all_values[7]	auto[0]	auto[0]	auto[0]	2746149	1			T32	2316		T1	39		T11	65
all_values[7]	auto[0]	auto[0]	auto[1]	6589151	1			T32	5460		T1	6		T11	12
all_values[7]	auto[0]	auto[1]	auto[0]	708416	1			T32	736		T1	5		T11	11
all_values[7]	auto[0]	auto[1]	auto[1]	6588717	1			T32	6228		T1	13		T11	5
all_values[7]	auto[1]	auto[0]	auto[1]	97219	1			T32	116		T1	1		T11	5
all_values[7]	auto[1]	auto[1]	auto[1]	96954	1			T32	117		T1	2		T11	1
all_values[8]	auto[0]	auto[0]	auto[0]	2750339	1			T32	1858		T1	39		T11	42
all_values[8]	auto[0]	auto[0]	auto[1]	6575361	1			T32	5183		T1	9		T11	14
all_values[8]	auto[0]	auto[1]	auto[0]	719601	1			T32	507		T1	6		T11	23
all_values[8]	auto[0]	auto[1]	auto[1]	6587207	1			T32	7183		T1	8		T11	12
all_values[8]	auto[1]	auto[0]	auto[1]	97126	1			T32	124		T1	3		T11	3
all_values[8]	auto[1]	auto[1]	auto[1]	96972	1			T32	118		T1	1		T11	5
all_values[9]	auto[0]	auto[0]	auto[0]	2744600	1			T32	1771		T1	27		T11	60
all_values[9]	auto[0]	auto[0]	auto[1]	6595970	1			T32	5603		T1	18		T11	6
all_values[9]	auto[0]	auto[1]	auto[0]	718643	1			T32	544		T1	8		T11	18
all_values[9]	auto[0]	auto[1]	auto[1]	6572717	1			T32	6810		T1	8		T11	7
all_values[9]	auto[1]	auto[0]	auto[1]	97841	1			T32	116		T1	4		T11	7
all_values[9]	auto[1]	auto[1]	auto[1]	96835	1			T32	129		T1	1		T11	1
all_values[10]	auto[0]	auto[0]	auto[0]	2756527	1			T32	1777		T1	41		T11	37
all_values[10]	auto[0]	auto[0]	auto[1]	6565220	1			T32	7143		T1	15		T11	26
all_values[10]	auto[0]	auto[1]	auto[0]	728923	1			T32	638		T1	5		T11	27
all_values[10]	auto[0]	auto[1]	auto[1]	6581895	1			T32	5152		T1	1		T11	1
all_values[10]	auto[1]	auto[0]	auto[1]	97471	1			T32	124		T1	4		T11	6
all_values[10]	auto[1]	auto[1]	auto[1]	96570	1			T32	139		T11	2		T13	2821
all_values[11]	auto[0]	auto[0]	auto[0]	2754056	1			T32	1745		T1	31		T11	46
all_values[11]	auto[0]	auto[0]	auto[1]	6564417	1			T32	7327		T1	23		T11	5
all_values[11]	auto[0]	auto[1]	auto[0]	717306	1			T32	719		T1	6		T11	19
all_values[11]	auto[0]	auto[1]	auto[1]	6596049	1			T32	4948		T11	21		T13	176920
all_values[11]	auto[1]	auto[0]	auto[1]	97572	1			T32	116		T1	6		T11	2
all_values[11]	auto[1]	auto[1]	auto[1]	97206	1			T32	118		T11	6		T13	2718
all_values[12]	auto[0]	auto[0]	auto[0]	2748912	1			T32	1781		T1	47		T11	37
all_values[12]	auto[0]	auto[0]	auto[1]	6580247	1			T32	6219		T1	11		T11	15
all_values[12]	auto[0]	auto[1]	auto[0]	715121	1			T32	705		T1	6		T11	38
all_values[12]	auto[0]	auto[1]	auto[1]	6588246	1			T32	6016		T11	5		T13	175596
all_values[12]	auto[1]	auto[0]	auto[1]	97107	1			T32	132		T1	2		T11	1
all_values[12]	auto[1]	auto[1]	auto[1]	96973	1			T32	120		T11	3		T13	2669
all_values[13]	auto[0]	auto[0]	auto[0]	2746271	1			T32	1865		T1	45		T11	37
all_values[13]	auto[0]	auto[0]	auto[1]	6577862	1			T32	6338		T1	13		T11	15
all_values[13]	auto[0]	auto[1]	auto[0]	715912	1			T32	541		T1	5		T11	26
all_values[13]	auto[0]	auto[1]	auto[1]	6592007	1			T32	5982		T1	1		T11	16
all_values[13]	auto[1]	auto[0]	auto[1]	97949	1			T32	136		T1	2		T11	2
all_values[13]	auto[1]	auto[1]	auto[1]	96605	1			T32	111		T11	3		T13	2697
all_values[14]	auto[0]	auto[0]	auto[0]	2746172	1			T32	1717		T1	26		T11	60
all_values[14]	auto[0]	auto[0]	auto[1]	6568719	1			T32	6167		T1	10		T11	19
all_values[14]	auto[0]	auto[1]	auto[0]	724280	1			T32	418		T1	4		T11	8
all_values[14]	auto[0]	auto[1]	auto[1]	6592948	1			T32	6401		T1	19		T11	3
all_values[14]	auto[1]	auto[0]	auto[1]	97388	1			T32	148		T1	4		T11	9
all_values[14]	auto[1]	auto[1]	auto[1]	97099	1			T32	122		T1	3		T13	2848
all_values[15]	auto[0]	auto[0]	auto[0]	2748172	1			T32	2626		T1	29		T11	45
all_values[15]	auto[0]	auto[0]	auto[1]	6571749	1			T32	5101		T1	7		T11	23
all_values[15]	auto[0]	auto[1]	auto[0]	729204	1			T32	617		T1	12		T11	20
all_values[15]	auto[0]	auto[1]	auto[1]	6582939	1			T32	6394		T1	10		T11	3
all_values[15]	auto[1]	auto[0]	auto[1]	97496	1			T32	138		T1	4		T11	4
all_values[15]	auto[1]	auto[1]	auto[1]	97046	1			T32	97		T1	4		T11	4
all_values[16]	auto[0]	auto[0]	auto[0]	2747255	1			T32	1866		T1	29		T11	47
all_values[16]	auto[0]	auto[0]	auto[1]	6587311	1			T32	5257		T1	8		T11	6
all_values[16]	auto[0]	auto[1]	auto[0]	714350	1			T32	1671		T1	10		T11	31
all_values[16]	auto[0]	auto[1]	auto[1]	6582964	1			T32	5939		T1	15		T11	10
all_values[16]	auto[1]	auto[0]	auto[1]	97479	1			T32	135		T1	3		T11	5
all_values[16]	auto[1]	auto[1]	auto[1]	97247	1			T32	105		T1	1		T13	2799
all_values[17]	auto[0]	auto[0]	auto[0]	2742882	1			T32	1703		T1	44		T11	41
all_values[17]	auto[0]	auto[0]	auto[1]	6603128	1			T32	6324		T1	3		T11	19
all_values[17]	auto[0]	auto[1]	auto[0]	710891	1			T32	546		T1	14		T11	28
all_values[17]	auto[0]	auto[1]	auto[1]	6575152	1			T32	6154		T1	3		T11	3
all_values[17]	auto[1]	auto[0]	auto[1]	97216	1			T32	134		T1	2		T11	5
all_values[17]	auto[1]	auto[1]	auto[1]	97337	1			T32	112		T11	3		T13	2797
all_values[18]	auto[0]	auto[0]	auto[0]	2741083	1			T32	1666		T1	37		T11	49
all_values[18]	auto[0]	auto[0]	auto[1]	6614951	1			T32	7070		T1	3		T11	1
all_values[18]	auto[0]	auto[1]	auto[0]	719499	1			T32	674		T1	18		T11	34
all_values[18]	auto[0]	auto[1]	auto[1]	6556627	1			T32	5305		T1	7		T11	9
all_values[18]	auto[1]	auto[0]	auto[1]	97457	1			T32	133		T11	2		T13	2672
all_values[18]	auto[1]	auto[1]	auto[1]	96989	1			T32	125		T1	1		T11	4
all_values[19]	auto[0]	auto[0]	auto[0]	2756580	1			T32	1699		T1	39		T11	37
all_values[19]	auto[0]	auto[0]	auto[1]	6575344	1			T32	5888		T1	8		T11	16
all_values[19]	auto[0]	auto[1]	auto[0]	713759	1			T32	536		T1	7		T11	29
all_values[19]	auto[0]	auto[1]	auto[1]	6586430	1			T32	6598		T1	8		T11	11
all_values[19]	auto[1]	auto[0]	auto[1]	97822	1			T32	123		T1	4		T11	5
all_values[19]	auto[1]	auto[1]	auto[1]	96671	1			T32	129		T11	1		T13	2746
all_values[20]	auto[0]	auto[0]	auto[0]	2745022	1			T32	1780		T1	31		T11	53
all_values[20]	auto[0]	auto[0]	auto[1]	6559399	1			T32	5921		T1	13		T11	16
all_values[20]	auto[0]	auto[1]	auto[0]	721922	1			T32	511		T1	4		T11	10
all_values[20]	auto[0]	auto[1]	auto[1]	6605607	1			T32	6517		T1	15		T11	12
all_values[20]	auto[1]	auto[0]	auto[1]	97800	1			T32	136		T1	2		T11	8
all_values[20]	auto[1]	auto[1]	auto[1]	96856	1			T32	108		T1	1		T13	2764
all_values[21]	auto[0]	auto[0]	auto[0]	2743797	1			T32	1709		T1	36		T11	45
all_values[21]	auto[0]	auto[0]	auto[1]	6563305	1			T32	6358		T1	27		T11	13
all_values[21]	auto[0]	auto[1]	auto[0]	706174	1			T32	564		T11	21		T13	18039
all_values[21]	auto[0]	auto[1]	auto[1]	6618070	1			T32	6099		T11	14		T13	180344
all_values[21]	auto[1]	auto[0]	auto[1]	97462	1			T32	115		T1	3		T11	4
all_values[21]	auto[1]	auto[1]	auto[1]	97798	1			T32	128		T11	2		T13	2812
all_values[22]	auto[0]	auto[0]	auto[0]	2756544	1			T32	2927		T1	31		T11	60
all_values[22]	auto[0]	auto[0]	auto[1]	6576316	1			T32	4582		T1	15		T11	14
all_values[22]	auto[0]	auto[1]	auto[0]	714889	1			T32	737		T1	8		T11	14
all_values[22]	auto[0]	auto[1]	auto[1]	6584120	1			T32	6477		T1	7		T11	6
all_values[22]	auto[1]	auto[0]	auto[1]	97717	1			T32	108		T1	3		T11	4
all_values[22]	auto[1]	auto[1]	auto[1]	97020	1			T32	142		T1	2		T11	1
all_values[23]	auto[0]	auto[0]	auto[0]	2738637	1			T32	1724		T1	31		T11	46
all_values[23]	auto[0]	auto[0]	auto[1]	6595469	1			T32	6639		T1	21		T11	11
all_values[23]	auto[0]	auto[1]	auto[0]	725774	1			T32	397		T1	11		T11	18
all_values[23]	auto[0]	auto[1]	auto[1]	6572635	1			T32	5974		T11	16		T13	176566
all_values[23]	auto[1]	auto[0]	auto[1]	97432	1			T32	137		T1	3		T11	3
all_values[23]	auto[1]	auto[1]	auto[1]	96659	1			T32	102		T11	5		T13	2643
all_values[24]	auto[0]	auto[0]	auto[0]	2745421	1			T32	1825		T1	33		T11	40
all_values[24]	auto[0]	auto[0]	auto[1]	6610084	1			T32	7289		T1	10		T11	27
all_values[24]	auto[0]	auto[1]	auto[0]	723655	1			T32	570		T1	12		T11	22
all_values[24]	auto[0]	auto[1]	auto[1]	6553319	1			T32	5044		T1	6		T11	3
all_values[24]	auto[1]	auto[0]	auto[1]	97364	1			T32	146		T1	3		T11	6
all_values[24]	auto[1]	auto[1]	auto[1]	96763	1			T32	99		T1	2		T11	1
all_values[25]	auto[0]	auto[0]	auto[0]	2752391	1			T32	1846		T1	47		T11	42
all_values[25]	auto[0]	auto[0]	auto[1]	6602821	1			T32	7135		T1	9		T11	18
all_values[25]	auto[0]	auto[1]	auto[0]	710254	1			T32	592		T1	7		T11	12
all_values[25]	auto[0]	auto[1]	auto[1]	6566751	1			T32	5160		T1	1		T11	15
all_values[25]	auto[1]	auto[0]	auto[1]	97476	1			T32	126		T1	1		T11	7
all_values[25]	auto[1]	auto[1]	auto[1]	96913	1			T32	114		T1	1		T11	5
all_values[26]	auto[0]	auto[0]	auto[0]	2753482	1			T32	1854		T1	37		T11	44
all_values[26]	auto[0]	auto[0]	auto[1]	6577484	1			T32	4986		T1	2		T11	17
all_values[26]	auto[0]	auto[1]	auto[0]	721278	1			T32	1619		T1	8		T11	26
all_values[26]	auto[0]	auto[1]	auto[1]	6580060	1			T32	6248		T1	16		T11	7
all_values[26]	auto[1]	auto[0]	auto[1]	97667	1			T32	140		T1	1		T11	4
all_values[26]	auto[1]	auto[1]	auto[1]	96635	1			T32	126		T1	2		T11	1
all_values[27]	auto[0]	auto[0]	auto[0]	2749074	1			T32	1760		T1	30		T11	66
all_values[27]	auto[0]	auto[0]	auto[1]	6610385	1			T32	4946		T1	15		T11	7
all_values[27]	auto[0]	auto[1]	auto[0]	725610	1			T32	640		T1	9		T11	14
all_values[27]	auto[0]	auto[1]	auto[1]	6546461	1			T32	7364		T1	7		T11	5
all_values[27]	auto[1]	auto[0]	auto[1]	97774	1			T32	136		T1	4		T11	4
all_values[27]	auto[1]	auto[1]	auto[1]	97302	1			T32	127		T1	1		T11	3
all_values[28]	auto[0]	auto[0]	auto[0]	2746162	1			T32	1715		T1	36		T11	41
all_values[28]	auto[0]	auto[0]	auto[1]	6555331	1			T32	6765		T1	7		T11	32
all_values[28]	auto[0]	auto[1]	auto[0]	722295	1			T32	633		T1	11		T11	9
all_values[28]	auto[0]	auto[1]	auto[1]	6608393	1			T32	5587		T1	8		T11	11
all_values[28]	auto[1]	auto[0]	auto[1]	97326	1			T32	141		T1	3		T11	5
all_values[28]	auto[1]	auto[1]	auto[1]	97099	1			T32	132		T1	1		T11	1
all_values[29]	auto[0]	auto[0]	auto[0]	2743481	1			T32	1827		T1	34		T11	36
all_values[29]	auto[0]	auto[0]	auto[1]	6592731	1			T32	7659		T1	5		T11	15
all_values[29]	auto[0]	auto[1]	auto[0]	718812	1			T32	502		T1	17		T11	25
all_values[29]	auto[0]	auto[1]	auto[1]	6576729	1			T32	4720		T1	7		T11	17
all_values[29]	auto[1]	auto[0]	auto[1]	98036	1			T32	119		T1	1		T11	3
all_values[29]	auto[1]	auto[1]	auto[1]	96817	1			T32	146		T1	2		T11	3
all_values[30]	auto[0]	auto[0]	auto[0]	2742560	1			T32	1818		T1	34		T11	61
all_values[30]	auto[0]	auto[0]	auto[1]	6569093	1			T32	4814		T1	4		T11	24
all_values[30]	auto[0]	auto[1]	auto[0]	725680	1			T32	583		T1	12		T11	7
all_values[30]	auto[0]	auto[1]	auto[1]	6594852	1			T32	7512		T1	12		T11	3
all_values[30]	auto[1]	auto[0]	auto[1]	97164	1			T32	117		T1	2		T11	4
all_values[30]	auto[1]	auto[1]	auto[1]	97257	1			T32	129		T1	2		T13	2791
all_values[31]	auto[0]	auto[0]	auto[0]	2746479	1			T32	2323		T1	27		T11	38
all_values[31]	auto[0]	auto[0]	auto[1]	6610440	1			T32	5082		T1	30		T11	28
all_values[31]	auto[0]	auto[1]	auto[0]	711149	1			T32	577		T1	5		T11	25
all_values[31]	auto[0]	auto[1]	auto[1]	6563867	1			T32	6730		T1	1		T11	2
all_values[31]	auto[1]	auto[0]	auto[1]	97625	1			T32	123		T1	3		T11	3
all_values[31]	auto[1]	auto[1]	auto[1]	97046	1			T32	138		T11	3		T13	2664

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal