Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[1]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[2]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[3]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[4]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[5]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[6]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[7]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[8]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[9]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[10]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[11]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[12]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[13]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[14]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[15]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[16]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[17]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[18]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[19]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[20]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[21]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[22]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[23]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[24]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[25]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[26]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[27]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[28]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[29]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[30]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[31]	16540798	1			T32	16779		T1	103		T11	176

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323713940

1

T32

155414

T1

1822

T11

2583

auto[1]

205591596

1

T32

381514

T1

1474

T11

3049

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

420280400

1

T32

375219

T1

3142

T11

5088

auto[1]

109025136

1

T32

161709

T1

154

T11

544

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

388401667

1

T32

326759

T1

2727

T11

4187

auto[1]

140903869

1

T32

210169

T1

569

T11

1445

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6142698	1			T32	2013		T1	37		T11	63
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4281184	1			T32	5316		T1	39		T11	59
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1719449	1			T32	2437		T11	4		T12	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2250028	1			T32	318		T1	10		T11	26
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	450702	1			T32	4045		T1	10		T11	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1696737	1			T32	2650		T1	7		T11	13
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6137494	1			T32	2109		T1	25		T11	51
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4284983	1			T32	5605		T1	46		T11	81
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1708374	1			T32	2716		T1	2		T11	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2259143	1			T32	226		T1	6		T11	19
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	450346	1			T32	3536		T1	5		T11	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1700458	1			T32	2587		T1	19		T11	6
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6143273	1			T32	2037		T1	50		T11	59
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4281364	1			T32	5768		T1	33		T11	81
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1716984	1			T32	2595		T11	1		T12	33
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2254315	1			T32	218		T1	13		T11	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	445963	1			T32	3719		T1	7		T11	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1698899	1			T32	2442		T11	5		T12	40
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6144807	1			T32	2019		T1	32		T11	39
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4279977	1			T32	5615		T1	51		T11	66
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1710153	1			T32	2484		T11	12		T12	36
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2255662	1			T32	276		T1	4		T11	40
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	449473	1			T32	3798		T1	4		T11	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1700726	1			T32	2587		T1	12		T11	6
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6136492	1			T32	2077		T1	56		T11	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4285365	1			T32	5544		T1	29		T11	73
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1711958	1			T32	2743		T11	8		T12	34
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2256223	1			T32	258		T1	10		T11	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	448837	1			T32	3630		T1	6		T11	24
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1701923	1			T32	2527		T1	2		T11	26
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6143102	1			T32	2125		T1	49		T11	37
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4275438	1			T32	5650		T1	32		T11	90
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1713716	1			T32	2362		T1	4		T11	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2260814	1			T32	219		T1	7		T11	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	449718	1			T32	3851		T1	6		T11	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1698010	1			T32	2572		T1	5		T11	20
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6152335	1			T32	2100		T1	41		T11	45
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4276353	1			T32	5672		T1	17		T11	63
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1717516	1			T32	2558		T11	10		T12	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2250059	1			T32	281		T1	29		T11	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	446276	1			T32	3695		T1	8		T11	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1698259	1			T32	2473		T1	8		T11	18
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6145118	1			T32	2037		T1	54		T11	47
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4278958	1			T32	5653		T1	41		T11	59
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1719062	1			T32	2350		T11	12		T12	51
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2251661	1			T32	277		T1	3		T11	35
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	449901	1			T32	3847		T1	2		T11	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1696098	1			T32	2615		T1	3		T11	6
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6148985	1			T32	2125		T1	63		T11	91
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4270301	1			T32	5863		T1	33		T11	49
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1716067	1			T32	2612		T1	2		T11	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2256490	1			T32	209		T1	5		T11	20
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	449855	1			T32	3548		T11	4		T13	4637
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1699100	1			T32	2422		T11	3		T12	37
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6137687	1			T32	2015		T1	26		T11	52
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4287872	1			T32	5342		T1	45		T11	63
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1713061	1			T32	2691		T11	28		T12	46
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2253964	1			T32	284		T1	13		T11	13
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	449253	1			T32	3859		T1	7		T11	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1698961	1			T32	2588		T1	12		T11	11
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6137322	1			T32	2069		T1	48		T11	16
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4287195	1			T32	5815		T1	45		T11	101
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1716447	1			T32	2454		T11	7		T12	26
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2250416	1			T32	240		T1	5		T11	18
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	448465	1			T32	3761		T1	2		T11	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1700953	1			T32	2440		T1	3		T11	17
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6148708	1			T32	2150		T1	65		T11	44
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4275041	1			T32	5478		T1	25		T11	70
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1713289	1			T32	2545		T11	11		T12	40
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2259101	1			T32	249		T1	12		T11	17
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	449274	1			T32	3730		T1	1		T11	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1695385	1			T32	2627		T11	9		T12	33
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6149179	1			T32	2063		T1	48		T11	45
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4268641	1			T32	5504		T1	37		T11	61
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1718500	1			T32	2425		T1	2		T11	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2256005	1			T32	275		T1	1		T11	31
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	448265	1			T32	3961		T1	10		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1700208	1			T32	2551		T1	5		T11	15
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6143222	1			T32	2059		T1	68		T11	33
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4277890	1			T32	5670		T1	23		T11	65
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1717532	1			T32	2587		T1	1		T11	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2255244	1			T32	241		T1	6		T11	32
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	448246	1			T32	3770		T1	2		T11	19
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1698664	1			T32	2452		T1	3		T11	23
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6146534	1			T32	2058		T1	38		T11	42
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4282172	1			T32	5786		T1	38		T11	57
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1713584	1			T32	2657		T11	15		T12	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2254629	1			T32	242		T1	3		T11	27
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	448167	1			T32	3433		T1	12		T11	21
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1695712	1			T32	2603		T1	12		T11	14
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6139450	1			T32	2057		T1	47		T11	67
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4281398	1			T32	5432		T1	19		T11	68
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1710039	1			T32	2558		T1	2		T11	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2257997	1			T32	279		T1	19		T11	28
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	448502	1			T32	3712		T1	10		T11	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1703412	1			T32	2741		T1	6		T11	6
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6157426	1			T32	2090		T1	41		T11	36
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4272837	1			T32	5600		T1	40		T11	89
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1708233	1			T32	2488		T1	2		T11	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2263512	1			T32	258		T1	12		T11	21
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	448658	1			T32	4015		T1	7		T11	25
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1690132	1			T32	2328		T1	1		T11	3
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6141450	1			T32	2078		T1	26		T11	65
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4282796	1			T32	5723		T1	63		T11	66
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1709104	1			T32	2591		T1	2		T11	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2262125	1			T32	252		T1	7		T11	19
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	452766	1			T32	3773		T1	5		T11	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1692557	1			T32	2362		T11	7		T12	26
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6144413	1			T32	2027		T1	55		T11	86
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4286416	1			T32	5189		T1	41		T11	29
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1707032	1			T32	2317		T1	4		T11	18
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2259203	1			T32	302		T1	3		T11	40
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	452077	1			T32	4205		T11	3		T13	4553
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1691657	1			T32	2739		T12	44		T13	44709
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6158409	1			T32	2054		T1	63		T11	41
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4276916	1			T32	5719		T1	24		T11	74
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1713325	1			T32	2594		T1	2		T11	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2254384	1			T32	225		T1	12		T11	37
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	446403	1			T32	3795		T1	2		T11	14
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1691361	1			T32	2392		T11	8		T12	43
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6150380	1			T32	2053		T1	52		T11	70
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4280906	1			T32	5690		T1	27		T11	63
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1705801	1			T32	2505		T1	3		T11	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2261041	1			T32	226		T1	19		T11	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	449524	1			T32	3764		T1	2		T11	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1693146	1			T32	2541		T11	17		T12	38
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6154173	1			T32	2062		T1	46		T11	73
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4278575	1			T32	5514		T1	38		T11	52
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1704131	1			T32	2510		T11	1		T12	38
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2264511	1			T32	249		T1	9		T11	23
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	452188	1			T32	3791		T1	7		T11	22
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1687220	1			T32	2653		T1	3		T11	5
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6161954	1			T32	2034		T1	38		T11	63
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4269107	1			T32	5560		T1	49		T11	82
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1707697	1			T32	2485		T11	1		T12	28
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2259085	1			T32	287		T1	8		T11	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	448523	1			T32	3818		T1	6		T11	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1694432	1			T32	2595		T1	2		T11	9
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6154177	1			T32	2042		T1	42		T11	23
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4273480	1			T32	5705		T1	45		T11	95
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1703117	1			T32	2416		T12	22		T13	44236
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2265032	1			T32	276		T1	8		T11	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	450579	1			T32	3733		T1	8		T11	30
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1694413	1			T32	2607		T11	14		T12	35
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6154318	1			T32	2049		T1	54		T11	62
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4274958	1			T32	5460		T1	43		T11	68
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1712043	1			T32	2633		T11	7		T12	32
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2256008	1			T32	252		T1	1		T11	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	447505	1			T32	3789		T1	3		T11	24
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1695966	1			T32	2596		T1	2		T11	11
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6133543	1			T32	2019		T1	52		T11	86
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4290621	1			T32	5462		T1	28		T11	49
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1711793	1			T32	2572		T1	9		T11	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2256977	1			T32	301		T1	13		T11	23
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	453917	1			T32	3986		T1	1		T11	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1693947	1			T32	2439		T11	9		T12	42
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6139311	1			T32	2045		T1	54		T11	17
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4282349	1			T32	5647		T1	40		T11	105
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1710768	1			T32	2664		T1	1		T11	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2263112	1			T32	288		T1	6		T11	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	452247	1			T32	3875		T1	2		T11	23
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1693011	1			T32	2260		T11	12		T12	38
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6155548	1			T32	2127		T1	40		T11	68
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4277063	1			T32	5433		T1	50		T11	89
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1708514	1			T32	2407		T11	7		T12	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2258609	1			T32	240		T1	6		T11	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	452364	1			T32	4171		T1	6		T11	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1688700	1			T32	2401		T1	1		T11	3
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6147745	1			T32	2107		T1	56		T11	21
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4276719	1			T32	5733		T1	23		T11	124
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1705507	1			T32	2491		T1	3		T11	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2265114	1			T32	208		T1	18		T11	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	450023	1			T32	3744		T1	3		T11	11
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1695690	1			T32	2496		T11	13		T12	38
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6156668	1			T32	2063		T1	58		T11	82
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4274522	1			T32	5849		T1	34		T11	37
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1711931	1			T32	2518		T11	2		T12	28
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2258556	1			T32	241		T1	6		T11	34
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	450406	1			T32	3659		T1	4		T11	17
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1688715	1			T32	2449		T1	1		T11	4
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6144879	1			T32	2064		T1	44		T11	58
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4282739	1			T32	6038		T1	45		T11	62
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1704621	1			T32	2588		T1	1		T11	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2261482	1			T32	226		T1	1		T11	34
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	449449	1			T32	3488		T1	6		T11	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1697628	1			T32	2375		T1	6		T11	4
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6145219	1			T32	2085		T1	22		T11	63
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4288285	1			T32	5525		T1	54		T11	93
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1703879	1			T32	2534		T11	3		T12	34
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2264192	1			T32	292		T1	17		T11	7
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	449394	1			T32	3831		T1	9		T11	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1689829	1			T32	2512		T1	1		T11	3

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal