Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[1]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[2]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[3]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[4]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[5]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[6]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[7]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[8]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[9]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[10]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[11]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[12]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[13]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[14]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[15]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[16]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[17]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[18]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[19]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[20]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[21]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[22]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[23]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[24]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[25]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[26]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[27]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[28]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[29]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[30]	16540798	1			T32	16779		T1	103		T11	176
bins_for_gpio_bits[31]	16540798	1			T32	16779		T1	103		T11	176

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323713940

1

T32

155414

T1

1822

T11

2583

auto[1]

205591596

1

T32

381514

T1

1474

T11

3049

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323705499

1

T32

155459

T1

1826

T11

2590

auto[1]

205600037

1

T32

381469

T1

1470

T11

3042

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9808710	1			T32	4303		T1	47		T11	93
bins_for_gpio_bits[0]	auto[0]	auto[1]	303190	1			T32	467		T12	10		T13	7747
bins_for_gpio_bits[0]	auto[1]	auto[0]	303465	1			T32	465		T12	10		T13	7747
bins_for_gpio_bits[0]	auto[1]	auto[1]	6125433	1			T32	11544		T1	56		T11	83
bins_for_gpio_bits[1]	auto[0]	auto[0]	9802218	1			T32	4577		T1	32		T11	74
bins_for_gpio_bits[1]	auto[0]	auto[1]	302558	1			T32	474		T1	2		T11	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	302793	1			T32	474		T1	1		T12	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	6133229	1			T32	11254		T1	68		T11	101
bins_for_gpio_bits[2]	auto[0]	auto[0]	9811142	1			T32	4349		T1	63		T11	86
bins_for_gpio_bits[2]	auto[0]	auto[1]	303161	1			T32	503		T12	10		T13	7770
bins_for_gpio_bits[2]	auto[1]	auto[0]	303430	1			T32	501		T12	10		T13	7771
bins_for_gpio_bits[2]	auto[1]	auto[1]	6123065	1			T32	11426		T1	40		T11	90
bins_for_gpio_bits[3]	auto[0]	auto[0]	9808426	1			T32	4311		T1	36		T11	91
bins_for_gpio_bits[3]	auto[0]	auto[1]	301939	1			T32	470		T1	1		T12	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	302196	1			T32	468		T12	11		T13	7777
bins_for_gpio_bits[3]	auto[1]	auto[1]	6128237	1			T32	11530		T1	66		T11	85
bins_for_gpio_bits[4]	auto[0]	auto[0]	9801314	1			T32	4590		T1	66		T11	53
bins_for_gpio_bits[4]	auto[0]	auto[1]	303113	1			T32	489		T11	1		T12	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	303359	1			T32	488		T12	10		T13	7748
bins_for_gpio_bits[4]	auto[1]	auto[1]	6133012	1			T32	11212		T1	37		T11	122
bins_for_gpio_bits[5]	auto[0]	auto[0]	9813879	1			T32	4251		T1	60		T11	59
bins_for_gpio_bits[5]	auto[0]	auto[1]	303487	1			T32	457		T11	2		T12	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	303753	1			T32	455		T11	1		T12	12
bins_for_gpio_bits[5]	auto[1]	auto[1]	6119679	1			T32	11616		T1	43		T11	114
bins_for_gpio_bits[6]	auto[0]	auto[0]	9817397	1			T32	4455		T1	70		T11	82
bins_for_gpio_bits[6]	auto[0]	auto[1]	302273	1			T32	487		T1	1		T12	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	302513	1			T32	484		T12	6		T13	7883
bins_for_gpio_bits[6]	auto[1]	auto[1]	6118615	1			T32	11353		T1	32		T11	94
bins_for_gpio_bits[7]	auto[0]	auto[0]	9812428	1			T32	4192		T1	57		T11	94
bins_for_gpio_bits[7]	auto[0]	auto[1]	303117	1			T32	474		T11	1		T12	12
bins_for_gpio_bits[7]	auto[1]	auto[0]	303413	1			T32	472		T12	12		T13	7808
bins_for_gpio_bits[7]	auto[1]	auto[1]	6121840	1			T32	11641		T1	46		T11	81
bins_for_gpio_bits[8]	auto[0]	auto[0]	9818031	1			T32	4458		T1	70		T11	120
bins_for_gpio_bits[8]	auto[0]	auto[1]	303239	1			T32	489		T12	9		T13	7801
bins_for_gpio_bits[8]	auto[1]	auto[0]	303511	1			T32	488		T12	10		T13	7802
bins_for_gpio_bits[8]	auto[1]	auto[1]	6116017	1			T32	11344		T1	33		T11	56
bins_for_gpio_bits[9]	auto[0]	auto[0]	9801863	1			T32	4512		T1	39		T11	92
bins_for_gpio_bits[9]	auto[0]	auto[1]	302604	1			T32	481		T1	1		T11	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	302849	1			T32	478		T11	1		T12	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	6133482	1			T32	11308		T1	63		T11	82
bins_for_gpio_bits[10]	auto[0]	auto[0]	9801131	1			T32	4299		T1	53		T11	41
bins_for_gpio_bits[10]	auto[0]	auto[1]	302791	1			T32	464		T12	10		T13	7803
bins_for_gpio_bits[10]	auto[1]	auto[0]	303054	1			T32	464		T12	11		T13	7803
bins_for_gpio_bits[10]	auto[1]	auto[1]	6133822	1			T32	11552		T1	50		T11	135
bins_for_gpio_bits[11]	auto[0]	auto[0]	9818541	1			T32	4481		T1	77		T11	72
bins_for_gpio_bits[11]	auto[0]	auto[1]	302260	1			T32	464		T11	1		T12	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	302557	1			T32	463		T12	10		T13	7721
bins_for_gpio_bits[11]	auto[1]	auto[1]	6117440	1			T32	11371		T1	26		T11	103
bins_for_gpio_bits[12]	auto[0]	auto[0]	9819607	1			T32	4310		T1	51		T11	89
bins_for_gpio_bits[12]	auto[0]	auto[1]	303835	1			T32	453		T11	1		T12	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	304077	1			T32	453		T12	5		T13	7948
bins_for_gpio_bits[12]	auto[1]	auto[1]	6113279	1			T32	11563		T1	52		T11	86
bins_for_gpio_bits[13]	auto[0]	auto[0]	9812703	1			T32	4395		T1	75		T11	69
bins_for_gpio_bits[13]	auto[0]	auto[1]	303024	1			T32	493		T11	1		T12	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	303295	1			T32	492		T12	9		T13	7888
bins_for_gpio_bits[13]	auto[1]	auto[1]	6121776	1			T32	11399		T1	28		T11	106
bins_for_gpio_bits[14]	auto[0]	auto[0]	9811898	1			T32	4464		T1	41		T11	84
bins_for_gpio_bits[14]	auto[0]	auto[1]	302608	1			T32	495		T11	1		T12	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	302849	1			T32	493		T12	9		T13	7730
bins_for_gpio_bits[14]	auto[1]	auto[1]	6123443	1			T32	11327		T1	62		T11	91
bins_for_gpio_bits[15]	auto[0]	auto[0]	9804799	1			T32	4419		T1	68		T11	99
bins_for_gpio_bits[15]	auto[0]	auto[1]	302392	1			T32	475		T12	13		T13	7785
bins_for_gpio_bits[15]	auto[1]	auto[0]	302687	1			T32	475		T12	13		T13	7785
bins_for_gpio_bits[15]	auto[1]	auto[1]	6130920	1			T32	11410		T1	35		T11	77
bins_for_gpio_bits[16]	auto[0]	auto[0]	9826265	1			T32	4397		T1	55		T11	59
bins_for_gpio_bits[16]	auto[0]	auto[1]	302655	1			T32	440		T12	7		T13	7782
bins_for_gpio_bits[16]	auto[1]	auto[0]	302906	1			T32	439		T12	8		T13	7782
bins_for_gpio_bits[16]	auto[1]	auto[1]	6108972	1			T32	11503		T1	48		T11	117
bins_for_gpio_bits[17]	auto[0]	auto[0]	9809888	1			T32	4444		T1	35		T11	88
bins_for_gpio_bits[17]	auto[0]	auto[1]	302517	1			T32	479		T12	8		T13	7879
bins_for_gpio_bits[17]	auto[1]	auto[0]	302791	1			T32	477		T12	8		T13	7879
bins_for_gpio_bits[17]	auto[1]	auto[1]	6125602	1			T32	11379		T1	68		T11	88
bins_for_gpio_bits[18]	auto[0]	auto[0]	9808089	1			T32	4201		T1	62		T11	142
bins_for_gpio_bits[18]	auto[0]	auto[1]	302290	1			T32	447		T11	2		T12	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	302559	1			T32	445		T11	2		T12	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	6127860	1			T32	11686		T1	41		T11	30
bins_for_gpio_bits[19]	auto[0]	auto[0]	9823308	1			T32	4400		T1	77		T11	80
bins_for_gpio_bits[19]	auto[0]	auto[1]	302526	1			T32	473		T12	10		T13	7782
bins_for_gpio_bits[19]	auto[1]	auto[0]	302810	1			T32	473		T12	11		T13	7783
bins_for_gpio_bits[19]	auto[1]	auto[1]	6112154	1			T32	11433		T1	26		T11	96
bins_for_gpio_bits[20]	auto[0]	auto[0]	9814313	1			T32	4308		T1	74		T11	85
bins_for_gpio_bits[20]	auto[0]	auto[1]	302646	1			T32	478		T12	10		T13	7906
bins_for_gpio_bits[20]	auto[1]	auto[0]	302909	1			T32	476		T12	10		T13	7906
bins_for_gpio_bits[20]	auto[1]	auto[1]	6120930	1			T32	11517		T1	29		T11	91
bins_for_gpio_bits[21]	auto[0]	auto[0]	9820509	1			T32	4364		T1	55		T11	97
bins_for_gpio_bits[21]	auto[0]	auto[1]	302061	1			T32	458		T12	11		T13	7763
bins_for_gpio_bits[21]	auto[1]	auto[0]	302306	1			T32	457		T12	11		T13	7764
bins_for_gpio_bits[21]	auto[1]	auto[1]	6115922	1			T32	11500		T1	48		T11	79
bins_for_gpio_bits[22]	auto[0]	auto[0]	9826060	1			T32	4341		T1	46		T11	78
bins_for_gpio_bits[22]	auto[0]	auto[1]	302407	1			T32	465		T12	5		T13	7840
bins_for_gpio_bits[22]	auto[1]	auto[0]	302676	1			T32	465		T12	6		T13	7840
bins_for_gpio_bits[22]	auto[1]	auto[1]	6109655	1			T32	11508		T1	57		T11	98
bins_for_gpio_bits[23]	auto[0]	auto[0]	9818934	1			T32	4264		T1	50		T11	37
bins_for_gpio_bits[23]	auto[0]	auto[1]	303122	1			T32	470		T12	9		T13	7750
bins_for_gpio_bits[23]	auto[1]	auto[0]	303392	1			T32	470		T12	10		T13	7751
bins_for_gpio_bits[23]	auto[1]	auto[1]	6115350	1			T32	11575		T1	53		T11	139
bins_for_gpio_bits[24]	auto[0]	auto[0]	9819422	1			T32	4473		T1	55		T11	72
bins_for_gpio_bits[24]	auto[0]	auto[1]	302653	1			T32	462		T12	10		T13	7798
bins_for_gpio_bits[24]	auto[1]	auto[0]	302947	1			T32	461		T11	1		T12	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	6115776	1			T32	11383		T1	48		T11	103
bins_for_gpio_bits[25]	auto[0]	auto[0]	9799410	1			T32	4422		T1	74		T11	112
bins_for_gpio_bits[25]	auto[0]	auto[1]	302662	1			T32	472		T12	10		T13	7850
bins_for_gpio_bits[25]	auto[1]	auto[0]	302903	1			T32	470		T12	10		T13	7850
bins_for_gpio_bits[25]	auto[1]	auto[1]	6135823	1			T32	11415		T1	29		T11	64
bins_for_gpio_bits[26]	auto[0]	auto[0]	9809682	1			T32	4521		T1	61		T11	36
bins_for_gpio_bits[26]	auto[0]	auto[1]	303239	1			T32	478		T12	10		T13	7903
bins_for_gpio_bits[26]	auto[1]	auto[0]	303509	1			T32	476		T12	10		T13	7904
bins_for_gpio_bits[26]	auto[1]	auto[1]	6124368	1			T32	11304		T1	42		T11	140
bins_for_gpio_bits[27]	auto[0]	auto[0]	9819530	1			T32	4313		T1	46		T11	79
bins_for_gpio_bits[27]	auto[0]	auto[1]	302880	1			T32	463		T12	11		T13	7873
bins_for_gpio_bits[27]	auto[1]	auto[0]	303141	1			T32	461		T12	11		T13	7874
bins_for_gpio_bits[27]	auto[1]	auto[1]	6115247	1			T32	11542		T1	57		T11	97
bins_for_gpio_bits[28]	auto[0]	auto[0]	9815330	1			T32	4332		T1	77		T11	27
bins_for_gpio_bits[28]	auto[0]	auto[1]	302760	1			T32	475		T11	1		T12	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	303036	1			T32	474		T11	1		T12	9
bins_for_gpio_bits[28]	auto[1]	auto[1]	6119672	1			T32	11498		T1	26		T11	147
bins_for_gpio_bits[29]	auto[0]	auto[0]	9824589	1			T32	4368		T1	64		T11	117
bins_for_gpio_bits[29]	auto[0]	auto[1]	302293	1			T32	458		T11	1		T12	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	302566	1			T32	454		T11	1		T12	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	6111350	1			T32	11499		T1	39		T11	57
bins_for_gpio_bits[30]	auto[0]	auto[0]	9807614	1			T32	4387		T1	46		T11	96
bins_for_gpio_bits[30]	auto[0]	auto[1]	303125	1			T32	492		T12	9		T13	7794
bins_for_gpio_bits[30]	auto[1]	auto[0]	303368	1			T32	491		T12	10		T13	7795
bins_for_gpio_bits[30]	auto[1]	auto[1]	6126691	1			T32	11409		T1	57		T11	80
bins_for_gpio_bits[31]	auto[0]	auto[0]	9810727	1			T32	4446		T1	39		T11	72
bins_for_gpio_bits[31]	auto[0]	auto[1]	302315	1			T32	467		T11	1		T12	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	302563	1			T32	465		T11	1		T12	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	6125193	1			T32	11401		T1	64		T11	102