Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446596 |
1 |
|
|
T32 |
8059 |
|
T1 |
51 |
|
T11 |
60 |
| auto[1] |
7380010 |
1 |
|
|
T32 |
6914 |
|
T1 |
15 |
|
T11 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15888476 |
1 |
|
|
T32 |
14321 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
938130 |
1 |
|
|
T32 |
652 |
|
T13 |
23953 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9428089 |
1 |
|
|
T32 |
8205 |
|
T1 |
47 |
|
T11 |
83 |
| auto[1] |
7398517 |
1 |
|
|
T32 |
6768 |
|
T1 |
19 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3235468 |
1 |
|
|
T32 |
3081 |
|
T1 |
10 |
|
T11 |
7 |
| auto[1] |
auto[0] |
auto[1] |
469915 |
1 |
|
|
T32 |
317 |
|
T13 |
12487 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3224919 |
1 |
|
|
T32 |
3035 |
|
T1 |
9 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[1] |
468215 |
1 |
|
|
T32 |
335 |
|
T13 |
11466 |
|
T2 |
1452 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9390096 |
1 |
|
|
T32 |
8390 |
|
T1 |
66 |
|
T11 |
59 |
| auto[1] |
7436510 |
1 |
|
|
T32 |
6583 |
|
T11 |
40 |
|
T13 |
203044 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15891193 |
1 |
|
|
T32 |
14081 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
935413 |
1 |
|
|
T32 |
892 |
|
T13 |
24559 |
|
T2 |
2591 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9436509 |
1 |
|
|
T32 |
6600 |
|
T1 |
53 |
|
T11 |
75 |
| auto[1] |
7390097 |
1 |
|
|
T32 |
8373 |
|
T1 |
13 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3216993 |
1 |
|
|
T32 |
3634 |
|
T1 |
13 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
466195 |
1 |
|
|
T32 |
417 |
|
T13 |
12229 |
|
T2 |
1230 |
| auto[1] |
auto[1] |
auto[0] |
3237691 |
1 |
|
|
T32 |
3847 |
|
T11 |
15 |
|
T13 |
86779 |
| auto[1] |
auto[1] |
auto[1] |
469218 |
1 |
|
|
T32 |
475 |
|
T13 |
12330 |
|
T2 |
1361 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9419218 |
1 |
|
|
T32 |
9044 |
|
T1 |
60 |
|
T11 |
69 |
| auto[1] |
7407388 |
1 |
|
|
T32 |
5929 |
|
T1 |
6 |
|
T11 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15895058 |
1 |
|
|
T32 |
14213 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
931548 |
1 |
|
|
T32 |
760 |
|
T13 |
25024 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9465974 |
1 |
|
|
T32 |
7549 |
|
T1 |
58 |
|
T11 |
91 |
| auto[1] |
7360632 |
1 |
|
|
T32 |
7424 |
|
T1 |
8 |
|
T11 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3224561 |
1 |
|
|
T32 |
3734 |
|
T1 |
8 |
|
T13 |
89423 |
| auto[1] |
auto[0] |
auto[1] |
467530 |
1 |
|
|
T32 |
459 |
|
T13 |
12733 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3204523 |
1 |
|
|
T32 |
2930 |
|
T11 |
8 |
|
T13 |
85653 |
| auto[1] |
auto[1] |
auto[1] |
464018 |
1 |
|
|
T32 |
301 |
|
T13 |
12291 |
|
T2 |
1135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9416045 |
1 |
|
|
T32 |
9188 |
|
T1 |
60 |
|
T11 |
53 |
| auto[1] |
7410561 |
1 |
|
|
T32 |
5785 |
|
T1 |
6 |
|
T11 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15897283 |
1 |
|
|
T32 |
14399 |
|
T1 |
64 |
|
T11 |
98 |
| auto[1] |
929323 |
1 |
|
|
T32 |
574 |
|
T1 |
2 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9476862 |
1 |
|
|
T32 |
8564 |
|
T1 |
37 |
|
T11 |
95 |
| auto[1] |
7349744 |
1 |
|
|
T32 |
6409 |
|
T1 |
29 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3209934 |
1 |
|
|
T32 |
3285 |
|
T1 |
27 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
463786 |
1 |
|
|
T32 |
373 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3210487 |
1 |
|
|
T32 |
2550 |
|
T13 |
87517 |
|
T16 |
8 |
| auto[1] |
auto[1] |
auto[1] |
465537 |
1 |
|
|
T32 |
201 |
|
T13 |
12445 |
|
T2 |
1413 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9426266 |
1 |
|
|
T32 |
8132 |
|
T1 |
60 |
|
T11 |
53 |
| auto[1] |
7400340 |
1 |
|
|
T32 |
6841 |
|
T1 |
6 |
|
T11 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15890083 |
1 |
|
|
T32 |
14215 |
|
T1 |
65 |
|
T11 |
98 |
| auto[1] |
936523 |
1 |
|
|
T32 |
758 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9439794 |
1 |
|
|
T32 |
7434 |
|
T1 |
47 |
|
T11 |
83 |
| auto[1] |
7386812 |
1 |
|
|
T32 |
7539 |
|
T1 |
19 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3227947 |
1 |
|
|
T32 |
3746 |
|
T1 |
18 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
468311 |
1 |
|
|
T32 |
417 |
|
T1 |
1 |
|
T13 |
12144 |
| auto[1] |
auto[1] |
auto[0] |
3222342 |
1 |
|
|
T32 |
3035 |
|
T11 |
12 |
|
T13 |
86863 |
| auto[1] |
auto[1] |
auto[1] |
468212 |
1 |
|
|
T32 |
341 |
|
T11 |
1 |
|
T13 |
12321 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9422082 |
1 |
|
|
T32 |
8339 |
|
T1 |
60 |
|
T11 |
54 |
| auto[1] |
7404524 |
1 |
|
|
T32 |
6634 |
|
T1 |
6 |
|
T11 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15890274 |
1 |
|
|
T32 |
14057 |
|
T1 |
64 |
|
T11 |
99 |
| auto[1] |
936332 |
1 |
|
|
T32 |
916 |
|
T1 |
2 |
|
T13 |
25115 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9431107 |
1 |
|
|
T32 |
6682 |
|
T1 |
44 |
|
T11 |
76 |
| auto[1] |
7395499 |
1 |
|
|
T32 |
8291 |
|
T1 |
22 |
|
T11 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3218860 |
1 |
|
|
T32 |
3879 |
|
T1 |
20 |
|
T11 |
7 |
| auto[1] |
auto[0] |
auto[1] |
464890 |
1 |
|
|
T32 |
465 |
|
T1 |
2 |
|
T13 |
12531 |
| auto[1] |
auto[1] |
auto[0] |
3240307 |
1 |
|
|
T32 |
3496 |
|
T11 |
16 |
|
T13 |
87834 |
| auto[1] |
auto[1] |
auto[1] |
471442 |
1 |
|
|
T32 |
451 |
|
T13 |
12584 |
|
T2 |
1503 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9412279 |
1 |
|
|
T32 |
8032 |
|
T1 |
40 |
|
T11 |
88 |
| auto[1] |
7414327 |
1 |
|
|
T32 |
6941 |
|
T1 |
26 |
|
T11 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15889842 |
1 |
|
|
T32 |
14498 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
936764 |
1 |
|
|
T32 |
475 |
|
T13 |
24812 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9426614 |
1 |
|
|
T32 |
9597 |
|
T1 |
52 |
|
T11 |
89 |
| auto[1] |
7399992 |
1 |
|
|
T32 |
5376 |
|
T1 |
14 |
|
T11 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3220239 |
1 |
|
|
T32 |
2481 |
|
T1 |
8 |
|
T11 |
10 |
| auto[1] |
auto[0] |
auto[1] |
466187 |
1 |
|
|
T32 |
214 |
|
T13 |
12435 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3242989 |
1 |
|
|
T32 |
2420 |
|
T1 |
6 |
|
T13 |
87776 |
| auto[1] |
auto[1] |
auto[1] |
470577 |
1 |
|
|
T32 |
261 |
|
T13 |
12377 |
|
T2 |
1362 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9417417 |
1 |
|
|
T32 |
7865 |
|
T1 |
40 |
|
T11 |
72 |
| auto[1] |
7409189 |
1 |
|
|
T32 |
7108 |
|
T1 |
26 |
|
T11 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15889771 |
1 |
|
|
T32 |
14284 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
936835 |
1 |
|
|
T32 |
689 |
|
T13 |
23879 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432321 |
1 |
|
|
T32 |
8235 |
|
T1 |
46 |
|
T11 |
81 |
| auto[1] |
7394285 |
1 |
|
|
T32 |
6738 |
|
T1 |
20 |
|
T11 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3228420 |
1 |
|
|
T32 |
2253 |
|
T1 |
11 |
|
T11 |
13 |
| auto[1] |
auto[0] |
auto[1] |
467879 |
1 |
|
|
T32 |
210 |
|
T13 |
11735 |
|
T2 |
1472 |
| auto[1] |
auto[1] |
auto[0] |
3229030 |
1 |
|
|
T32 |
3796 |
|
T1 |
9 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
468956 |
1 |
|
|
T32 |
479 |
|
T13 |
12144 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432045 |
1 |
|
|
T32 |
7258 |
|
T1 |
40 |
|
T11 |
58 |
| auto[1] |
7394561 |
1 |
|
|
T32 |
7715 |
|
T1 |
26 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15888413 |
1 |
|
|
T32 |
14486 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
938193 |
1 |
|
|
T32 |
487 |
|
T13 |
24549 |
|
T2 |
2661 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9421337 |
1 |
|
|
T32 |
9399 |
|
T1 |
37 |
|
T11 |
81 |
| auto[1] |
7405269 |
1 |
|
|
T32 |
5574 |
|
T1 |
29 |
|
T11 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3236790 |
1 |
|
|
T32 |
2434 |
|
T1 |
10 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
469841 |
1 |
|
|
T32 |
222 |
|
T13 |
12229 |
|
T2 |
1219 |
| auto[1] |
auto[1] |
auto[0] |
3230286 |
1 |
|
|
T32 |
2653 |
|
T1 |
19 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[1] |
468352 |
1 |
|
|
T32 |
265 |
|
T13 |
12320 |
|
T2 |
1442 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443226 |
1 |
|
|
T32 |
8161 |
|
T1 |
49 |
|
T11 |
65 |
| auto[1] |
7383380 |
1 |
|
|
T32 |
6812 |
|
T1 |
17 |
|
T11 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15889957 |
1 |
|
|
T32 |
14240 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
936649 |
1 |
|
|
T32 |
733 |
|
T13 |
23851 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9433878 |
1 |
|
|
T32 |
7944 |
|
T1 |
46 |
|
T11 |
88 |
| auto[1] |
7392728 |
1 |
|
|
T32 |
7029 |
|
T1 |
20 |
|
T11 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3243625 |
1 |
|
|
T32 |
3351 |
|
T1 |
20 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
470845 |
1 |
|
|
T32 |
393 |
|
T13 |
11814 |
|
T2 |
1307 |
| auto[1] |
auto[1] |
auto[0] |
3212454 |
1 |
|
|
T32 |
2945 |
|
T13 |
85024 |
|
T16 |
15 |
| auto[1] |
auto[1] |
auto[1] |
465804 |
1 |
|
|
T32 |
340 |
|
T13 |
12037 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9453491 |
1 |
|
|
T32 |
8869 |
|
T1 |
40 |
|
T11 |
52 |
| auto[1] |
7373115 |
1 |
|
|
T32 |
6104 |
|
T1 |
26 |
|
T11 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15885563 |
1 |
|
|
T32 |
14218 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
941043 |
1 |
|
|
T32 |
755 |
|
T1 |
1 |
|
T13 |
25227 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9408435 |
1 |
|
|
T32 |
7555 |
|
T1 |
55 |
|
T11 |
76 |
| auto[1] |
7418171 |
1 |
|
|
T32 |
7418 |
|
T1 |
11 |
|
T11 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3248168 |
1 |
|
|
T32 |
4182 |
|
T1 |
5 |
|
T11 |
8 |
| auto[1] |
auto[0] |
auto[1] |
472140 |
1 |
|
|
T32 |
513 |
|
T13 |
12634 |
|
T2 |
1373 |
| auto[1] |
auto[1] |
auto[0] |
3228960 |
1 |
|
|
T32 |
2481 |
|
T1 |
5 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[1] |
468903 |
1 |
|
|
T32 |
242 |
|
T1 |
1 |
|
T13 |
12593 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9429746 |
1 |
|
|
T32 |
7710 |
|
T1 |
51 |
|
T11 |
58 |
| auto[1] |
7396860 |
1 |
|
|
T32 |
7263 |
|
T1 |
15 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15892493 |
1 |
|
|
T32 |
14159 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
934113 |
1 |
|
|
T32 |
814 |
|
T13 |
24855 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446109 |
1 |
|
|
T32 |
7121 |
|
T1 |
59 |
|
T11 |
79 |
| auto[1] |
7380497 |
1 |
|
|
T32 |
7852 |
|
T1 |
7 |
|
T11 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3214249 |
1 |
|
|
T32 |
3031 |
|
T1 |
7 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
464095 |
1 |
|
|
T32 |
303 |
|
T13 |
12361 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3232135 |
1 |
|
|
T32 |
4007 |
|
T11 |
9 |
|
T13 |
87316 |
| auto[1] |
auto[1] |
auto[1] |
470018 |
1 |
|
|
T32 |
511 |
|
T13 |
12494 |
|
T2 |
1256 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9445066 |
1 |
|
|
T32 |
7638 |
|
T1 |
60 |
|
T11 |
58 |
| auto[1] |
7381540 |
1 |
|
|
T32 |
7335 |
|
T1 |
6 |
|
T11 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15893664 |
1 |
|
|
T32 |
14038 |
|
T1 |
66 |
|
T11 |
98 |
| auto[1] |
932942 |
1 |
|
|
T32 |
935 |
|
T11 |
1 |
|
T13 |
23706 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9461254 |
1 |
|
|
T32 |
6763 |
|
T1 |
44 |
|
T11 |
86 |
| auto[1] |
7365352 |
1 |
|
|
T32 |
8210 |
|
T1 |
22 |
|
T11 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3220433 |
1 |
|
|
T32 |
3221 |
|
T1 |
22 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
466791 |
1 |
|
|
T32 |
410 |
|
T11 |
1 |
|
T13 |
11800 |
| auto[1] |
auto[1] |
auto[0] |
3211977 |
1 |
|
|
T32 |
4054 |
|
T11 |
8 |
|
T13 |
84121 |
| auto[1] |
auto[1] |
auto[1] |
466151 |
1 |
|
|
T32 |
525 |
|
T13 |
11906 |
|
T2 |
1362 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9402221 |
1 |
|
|
T32 |
7837 |
|
T1 |
46 |
|
T11 |
77 |
| auto[1] |
7424385 |
1 |
|
|
T32 |
7136 |
|
T1 |
20 |
|
T11 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15892774 |
1 |
|
|
T32 |
14328 |
|
T1 |
62 |
|
T11 |
99 |
| auto[1] |
933832 |
1 |
|
|
T32 |
645 |
|
T1 |
4 |
|
T13 |
24051 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9445244 |
1 |
|
|
T32 |
8269 |
|
T1 |
37 |
|
T11 |
76 |
| auto[1] |
7381362 |
1 |
|
|
T32 |
6704 |
|
T1 |
29 |
|
T11 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3198187 |
1 |
|
|
T32 |
3394 |
|
T1 |
12 |
|
T11 |
16 |
| auto[1] |
auto[0] |
auto[1] |
462574 |
1 |
|
|
T32 |
361 |
|
T1 |
2 |
|
T13 |
12106 |
| auto[1] |
auto[1] |
auto[0] |
3249343 |
1 |
|
|
T32 |
2665 |
|
T1 |
13 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[1] |
471258 |
1 |
|
|
T32 |
284 |
|
T1 |
2 |
|
T13 |
11945 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9404564 |
1 |
|
|
T32 |
8182 |
|
T1 |
66 |
|
T11 |
62 |
| auto[1] |
7422042 |
1 |
|
|
T32 |
6791 |
|
T11 |
37 |
|
T13 |
201195 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15882543 |
1 |
|
|
T32 |
14078 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
944063 |
1 |
|
|
T32 |
895 |
|
T1 |
1 |
|
T13 |
23676 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9386192 |
1 |
|
|
T32 |
6791 |
|
T1 |
46 |
|
T11 |
90 |
| auto[1] |
7440414 |
1 |
|
|
T32 |
8182 |
|
T1 |
20 |
|
T11 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3250586 |
1 |
|
|
T32 |
4013 |
|
T1 |
19 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
472588 |
1 |
|
|
T32 |
480 |
|
T1 |
1 |
|
T13 |
11748 |
| auto[1] |
auto[1] |
auto[0] |
3245765 |
1 |
|
|
T32 |
3274 |
|
T11 |
5 |
|
T13 |
84723 |
| auto[1] |
auto[1] |
auto[1] |
471475 |
1 |
|
|
T32 |
415 |
|
T13 |
11928 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9430577 |
1 |
|
|
T32 |
7617 |
|
T1 |
49 |
|
T11 |
78 |
| auto[1] |
7396029 |
1 |
|
|
T32 |
7356 |
|
T1 |
17 |
|
T11 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15889116 |
1 |
|
|
T32 |
14401 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
937490 |
1 |
|
|
T32 |
572 |
|
T13 |
24504 |
|
T2 |
2709 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9424520 |
1 |
|
|
T32 |
8791 |
|
T1 |
56 |
|
T11 |
84 |
| auto[1] |
7402086 |
1 |
|
|
T32 |
6182 |
|
T1 |
10 |
|
T11 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3220290 |
1 |
|
|
T32 |
2566 |
|
T1 |
4 |
|
T11 |
10 |
| auto[1] |
auto[0] |
auto[1] |
465239 |
1 |
|
|
T32 |
265 |
|
T13 |
11473 |
|
T2 |
1341 |
| auto[1] |
auto[1] |
auto[0] |
3244306 |
1 |
|
|
T32 |
3044 |
|
T1 |
6 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
472251 |
1 |
|
|
T32 |
307 |
|
T13 |
13031 |
|
T2 |
1368 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9431538 |
1 |
|
|
T32 |
8500 |
|
T1 |
55 |
|
T11 |
60 |
| auto[1] |
7395068 |
1 |
|
|
T32 |
6473 |
|
T1 |
11 |
|
T11 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15886318 |
1 |
|
|
T32 |
14297 |
|
T1 |
65 |
|
T11 |
98 |
| auto[1] |
940288 |
1 |
|
|
T32 |
676 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9400452 |
1 |
|
|
T32 |
8135 |
|
T1 |
34 |
|
T11 |
89 |
| auto[1] |
7426154 |
1 |
|
|
T32 |
6838 |
|
T1 |
32 |
|
T11 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3249361 |
1 |
|
|
T32 |
2841 |
|
T1 |
21 |
|
T11 |
9 |
| auto[1] |
auto[0] |
auto[1] |
472374 |
1 |
|
|
T32 |
274 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3236505 |
1 |
|
|
T32 |
3321 |
|
T1 |
10 |
|
T13 |
86054 |
| auto[1] |
auto[1] |
auto[1] |
467914 |
1 |
|
|
T32 |
402 |
|
T13 |
12236 |
|
T2 |
1533 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452869 |
1 |
|
|
T32 |
9260 |
|
T1 |
46 |
|
T11 |
73 |
| auto[1] |
7373737 |
1 |
|
|
T32 |
5713 |
|
T1 |
20 |
|
T11 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15893945 |
1 |
|
|
T32 |
14189 |
|
T1 |
65 |
|
T11 |
98 |
| auto[1] |
932661 |
1 |
|
|
T32 |
784 |
|
T1 |
1 |
|
T11 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454202 |
1 |
|
|
T32 |
6894 |
|
T1 |
33 |
|
T11 |
81 |
| auto[1] |
7372404 |
1 |
|
|
T32 |
8079 |
|
T1 |
33 |
|
T11 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3232116 |
1 |
|
|
T32 |
4928 |
|
T1 |
13 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
469332 |
1 |
|
|
T32 |
580 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3207627 |
1 |
|
|
T32 |
2367 |
|
T1 |
19 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[1] |
463329 |
1 |
|
|
T32 |
204 |
|
T13 |
12856 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452688 |
1 |
|
|
T32 |
9107 |
|
T1 |
57 |
|
T11 |
67 |
| auto[1] |
7373918 |
1 |
|
|
T32 |
5866 |
|
T1 |
9 |
|
T11 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15893233 |
1 |
|
|
T32 |
14201 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
933373 |
1 |
|
|
T32 |
772 |
|
T13 |
23390 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9448457 |
1 |
|
|
T32 |
7746 |
|
T1 |
39 |
|
T11 |
85 |
| auto[1] |
7378149 |
1 |
|
|
T32 |
7227 |
|
T1 |
27 |
|
T11 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3219616 |
1 |
|
|
T32 |
3571 |
|
T1 |
18 |
|
T11 |
10 |
| auto[1] |
auto[0] |
auto[1] |
466324 |
1 |
|
|
T32 |
433 |
|
T13 |
11352 |
|
T2 |
1351 |
| auto[1] |
auto[1] |
auto[0] |
3225160 |
1 |
|
|
T32 |
2884 |
|
T1 |
9 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[1] |
467049 |
1 |
|
|
T32 |
339 |
|
T13 |
12038 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9428633 |
1 |
|
|
T32 |
6980 |
|
T1 |
40 |
|
T11 |
65 |
| auto[1] |
7397973 |
1 |
|
|
T32 |
7993 |
|
T1 |
26 |
|
T11 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15892961 |
1 |
|
|
T32 |
14308 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
933645 |
1 |
|
|
T32 |
665 |
|
T1 |
1 |
|
T13 |
24431 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454967 |
1 |
|
|
T32 |
8353 |
|
T1 |
48 |
|
T11 |
89 |
| auto[1] |
7371639 |
1 |
|
|
T32 |
6620 |
|
T1 |
18 |
|
T11 |
10 |