Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9442894 |
1 |
|
|
T32 |
7787 |
|
T1 |
51 |
|
T11 |
65 |
| auto[1] |
7383712 |
1 |
|
|
T32 |
7186 |
|
T1 |
15 |
|
T11 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15896785 |
1 |
|
|
T32 |
14545 |
|
T1 |
66 |
|
T11 |
99 |
| auto[1] |
929821 |
1 |
|
|
T32 |
428 |
|
T13 |
24464 |
|
T2 |
2869 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9461139 |
1 |
|
|
T32 |
9574 |
|
T1 |
33 |
|
T11 |
87 |
| auto[1] |
7365467 |
1 |
|
|
T32 |
5399 |
|
T1 |
33 |
|
T11 |
12 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3222596 |
1 |
|
|
T32 |
2614 |
|
T1 |
24 |
|
T11 |
5 |
| auto[1] |
auto[0] |
auto[1] |
465338 |
1 |
|
|
T32 |
220 |
|
T13 |
11669 |
|
T2 |
1331 |
| auto[1] |
auto[1] |
auto[0] |
3213050 |
1 |
|
|
T32 |
2357 |
|
T1 |
9 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[1] |
464483 |
1 |
|
|
T32 |
208 |
|
T13 |
12795 |
|
T2 |
1538 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |