Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9419467 |
1 |
|
|
T32 |
8988 |
|
T1 |
49 |
|
T11 |
66 |
| auto[1] |
7407139 |
1 |
|
|
T32 |
5985 |
|
T1 |
17 |
|
T11 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15891196 |
1 |
|
|
T32 |
14175 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
935410 |
1 |
|
|
T32 |
798 |
|
T1 |
1 |
|
T13 |
24089 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9439923 |
1 |
|
|
T32 |
7635 |
|
T1 |
38 |
|
T11 |
93 |
| auto[1] |
7386683 |
1 |
|
|
T32 |
7338 |
|
T1 |
28 |
|
T11 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3228160 |
1 |
|
|
T32 |
3988 |
|
T1 |
23 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
468751 |
1 |
|
|
T32 |
534 |
|
T1 |
1 |
|
T13 |
12021 |
| auto[1] |
auto[1] |
auto[0] |
3223113 |
1 |
|
|
T32 |
2552 |
|
T1 |
4 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[1] |
466659 |
1 |
|
|
T32 |
264 |
|
T13 |
12068 |
|
T2 |
1337 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |