Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9422826 |
1 |
|
|
T32 |
7165 |
|
T1 |
51 |
|
T11 |
59 |
| auto[1] |
7403780 |
1 |
|
|
T32 |
7808 |
|
T1 |
15 |
|
T11 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15885137 |
1 |
|
|
T32 |
14267 |
|
T1 |
65 |
|
T11 |
99 |
| auto[1] |
941469 |
1 |
|
|
T32 |
706 |
|
T1 |
1 |
|
T13 |
23885 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9396188 |
1 |
|
|
T32 |
8279 |
|
T1 |
36 |
|
T11 |
88 |
| auto[1] |
7430418 |
1 |
|
|
T32 |
6694 |
|
T1 |
30 |
|
T11 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3244096 |
1 |
|
|
T32 |
2866 |
|
T1 |
20 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
471547 |
1 |
|
|
T32 |
303 |
|
T1 |
1 |
|
T13 |
12039 |
| auto[1] |
auto[1] |
auto[0] |
3244853 |
1 |
|
|
T32 |
3122 |
|
T1 |
9 |
|
T13 |
85663 |
| auto[1] |
auto[1] |
auto[1] |
469922 |
1 |
|
|
T32 |
403 |
|
T13 |
11846 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |