Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9438411 |
1 |
|
|
T32 |
7490 |
|
T1 |
49 |
|
T11 |
73 |
| auto[1] |
7388195 |
1 |
|
|
T32 |
7483 |
|
T1 |
17 |
|
T11 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15886577 |
1 |
|
|
T32 |
14517 |
|
T1 |
64 |
|
T11 |
99 |
| auto[1] |
940029 |
1 |
|
|
T32 |
456 |
|
T1 |
2 |
|
T13 |
23975 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9414904 |
1 |
|
|
T32 |
9681 |
|
T1 |
38 |
|
T11 |
79 |
| auto[1] |
7411702 |
1 |
|
|
T32 |
5292 |
|
T1 |
28 |
|
T11 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3235866 |
1 |
|
|
T32 |
2344 |
|
T1 |
17 |
|
T11 |
15 |
| auto[1] |
auto[0] |
auto[1] |
468898 |
1 |
|
|
T32 |
181 |
|
T1 |
1 |
|
T13 |
11624 |
| auto[1] |
auto[1] |
auto[0] |
3235807 |
1 |
|
|
T32 |
2492 |
|
T1 |
9 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
471131 |
1 |
|
|
T32 |
275 |
|
T1 |
1 |
|
T13 |
12351 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |