Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446596 |
1 |
|
|
T32 |
8059 |
|
T1 |
51 |
|
T11 |
60 |
| auto[1] |
7380010 |
1 |
|
|
T32 |
6914 |
|
T1 |
15 |
|
T11 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13829151 |
1 |
|
|
T32 |
10410 |
|
T1 |
61 |
|
T11 |
85 |
| auto[1] |
2997455 |
1 |
|
|
T32 |
4563 |
|
T1 |
5 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9366653 |
1 |
|
|
T32 |
8012 |
|
T1 |
60 |
|
T11 |
83 |
| auto[1] |
7459953 |
1 |
|
|
T32 |
6961 |
|
T1 |
6 |
|
T11 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243862 |
1 |
|
|
T32 |
988 |
|
T11 |
2 |
|
T13 |
65500 |
| auto[1] |
auto[0] |
auto[1] |
1502322 |
1 |
|
|
T32 |
1720 |
|
T1 |
3 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2218636 |
1 |
|
|
T32 |
1410 |
|
T1 |
1 |
|
T13 |
59847 |
| auto[1] |
auto[1] |
auto[1] |
1495133 |
1 |
|
|
T32 |
2843 |
|
T1 |
2 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |