Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9390096 |
1 |
|
|
T32 |
8390 |
|
T1 |
66 |
|
T11 |
59 |
| auto[1] |
7436510 |
1 |
|
|
T32 |
6583 |
|
T11 |
40 |
|
T13 |
203044 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13840457 |
1 |
|
|
T32 |
9808 |
|
T1 |
64 |
|
T11 |
77 |
| auto[1] |
2986149 |
1 |
|
|
T32 |
5165 |
|
T1 |
2 |
|
T11 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9413902 |
1 |
|
|
T32 |
7210 |
|
T1 |
63 |
|
T11 |
68 |
| auto[1] |
7412704 |
1 |
|
|
T32 |
7763 |
|
T1 |
3 |
|
T11 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2193939 |
1 |
|
|
T32 |
1335 |
|
T1 |
1 |
|
T11 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1484202 |
1 |
|
|
T32 |
2877 |
|
T1 |
2 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
2232616 |
1 |
|
|
T32 |
1263 |
|
T11 |
2 |
|
T13 |
67602 |
| auto[1] |
auto[1] |
auto[1] |
1501947 |
1 |
|
|
T32 |
2288 |
|
T11 |
13 |
|
T13 |
39100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |